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PPU: implement a cycle-accurate renderer (Version 2.0) #276

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merged 92 commits into from
Feb 23, 2023

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@fleroviux fleroviux commented Feb 11, 2023

This PR implements cycle-accurate emulation for the PPU.
The goal is to be as close as possible to real hardware. However despite my effort to reverse-engineer the PPU, some details remain unknown. So for now some inaccuracies will still exist that probably can be ironed out in the future.

This PR supersedes #258 (an earlier attempt at implementing my findings)

TODO

  • implement mosaic
  • DMAs should not trigger while the CPU is being stalled by the PPU
  • figure out the DISPCNT latch mess
  • implement forced-blank bit
  • fix bugs due to state updates that happen at the start of h-blank (i.e. affine registers)
  • do 2nd layer palette lookup two cycles later
  • handle the 6-th green channel bit during blending
  • do not sync the PPU on every IO write (even non-PPU IO)
  • adjust scanline timings to be exact (optional) (can be done after this PR)
  • implement save states
  • optimize code
  • cleanup code
  • perform regression tests

@fleroviux fleroviux changed the title WIP: PPU: implement a cycle-accurate renderer (Version 2.0) PPU: implement a cycle-accurate renderer (Version 2.0) Feb 23, 2023
@fleroviux fleroviux merged commit ded9888 into master Feb 23, 2023
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