zynq-7000

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Simple safe lock mechanism written in SystemVerilog.

oled systemverilog hdl zedboard xilinx-vivado zynq-7000

Fully connected dense neural network in SystemVerilog, synthesisable to an FPGA for neural network computation acceleration

fpga neural-network rtl xilinx vivado zynq-7000

Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

sdk fpga hardware accelerator matrix project matrix-multiplication verilog xilinx vivado systemverilog hardware-designs hdl hardware-acceleration zynq-7000 systolic-arrays pynq-z2 vitis

VHDL implementation of VGA controller. Implemented on Zybo Zynq-7000 board which uses switches to change output color.

vhdl vivado zybo zynq-7000 vga-controller

Notes after working with Zynq platform using vivado and petalinux

linux xilinx vivado systemverilog soc petalinux dma zynq-7000 axi-stream

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