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Add software-check exception text
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@aswaterman
aswaterman committed Oct 26, 2023
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Expand Up @@ -1815,6 +1815,15 @@ other instruction address exceptions.

[NOTE]
====
A Software Check exception is a synchronous exception that is triggered when
there are violations of checks and assertions defined by ISA extensions that
aim to safeguard the integrity of software assets, including e.g. control-flow
and memory-access constraints. When this exception is raised, the `__x__tval`
register is set either to 0 or to an informative value defined by the extension
that stipulated the exception be raised. The priority of this exception,
relative to other synchronous exceptions, depends on the cause of this exception
and is defined by the extension that stipulated the exception be raised.
A Hardware Error exception is a synchronous exception triggered when corrupted or
uncorrectable data is accessed explicitly or implicitly by an instruction. In
this context, "data" encompasses all types of information used within a RISC-V
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7 comments on commit 230bb41

@sorear
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@sorear sorear commented on 230bb41 Jan 26, 2024

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Is there intended to be a table here or a point of truth somewhere else documenting what the "informative values" mean and ensuring that they do not conflict? We have at least 2 and 3 being used by unratified specifications.

@gfavor
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@gfavor gfavor commented on 230bb41 Jan 26, 2024

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No, there is not an a priori table foreseeing the future of what the "informative values" shall be. This situation is analogous to reserved opcodes, reserved CSR numbers, and all other things with reserved values. And the same issue arises as to how does RISC-V avoid assignment conflicts for any of these things - which is one of the responsibilities of the ISA Committees and the Arch Review Committee to manage (and avoid conflicts).

@sorear
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@sorear sorear commented on 230bb41 Jan 26, 2024

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To be clear, I'm asking for a table of informative values that ARC has already allocated, not a table of values that ARC will allocate in the future. At the very least, a table of values that are used by ratified specifications.

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@gfavor gfavor commented on 230bb41 Jan 26, 2024

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That makes sense. Since there are no uses yet by any ratified specs, that's yet to come. At which point some discussion (by the ISA committees) will happen (in light of the actual first use cases) about what should be documented where, with what cross references, regarding specific use cases for this cause code.

@allenjbaum
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@allenjbaum allenjbaum commented on 230bb41 Jan 26, 2024 via email

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@sorear
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@sorear sorear commented on 230bb41 Jan 26, 2024

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There's already general text in the mtval register description allowing implementations to write 0 instead of the specific error for any type of trap unless contradicted by a profile; I think that covers your request.

riscv/riscv-cfi#137 says that value 1 is reserved, but doesn't go into the process beyond that.

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@ved-rivos ved-rivos commented on 230bb41 Jan 26, 2024 •
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Here is a thread with some background discussion on this topic. It was originally proposed for the value of 1 to indicate that an internal/RAS error occured. Following discussion in this thread it was agreed that it is not a good idea to mix RAS errors with software check and the value of 1 was dropped but it was suggested to keep it reserved.

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