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[AMDGPU] Fix unreachable reg bit width #122107

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merged 11 commits into from
Jan 22, 2025
+17 −0
Merged

[AMDGPU] Fix unreachable reg bit width #122107

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cfbc8ad
fix unreachable reg bit width. need add test case latter
Shoreshen Jan 8, 2025
a083e08
Merge remote-tracking branch 'origin/main' into Add-register-class-bi…
Shoreshen Jan 10, 2025
163fcc1
add test case, hard to find case forind case for SReg_128_XNULL & mer…
Shoreshen Jan 10, 2025
89e1047
fix lit.cfg.py
Shoreshen Jan 10, 2025
b1eddc3
run single pass
Shoreshen Jan 10, 2025
64378c4
fix lit
Shoreshen Jan 10, 2025
61cde04
Merge branch 'llvm:main' into Add-register-class-bit-width-for-SReg_2…
Shoreshen Jan 13, 2025
b971e70
Merge branch 'llvm:main' into Add-register-class-bit-width-for-SReg_2…
Shoreshen Jan 20, 2025
5706df1
Merge branch 'llvm:main' into Add-register-class-bit-width-for-SReg_2…
Shoreshen Jan 21, 2025
6b9cfce
add FIXME in test case
Shoreshen Jan 22, 2025
614c83d
Rename test
arsenm Jan 22, 2025
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2 changes: 2 additions & 0 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2487,6 +2487,7 @@ unsigned getRegBitWidth(unsigned RCID) {
case AMDGPU::AReg_128_Align2RegClassID:
case AMDGPU::AV_128RegClassID:
case AMDGPU::AV_128_Align2RegClassID:
case AMDGPU::SReg_128_XNULLRegClassID:
return 128;
case AMDGPU::SGPR_160RegClassID:
case AMDGPU::SReg_160RegClassID:
Expand Down Expand Up @@ -2523,6 +2524,7 @@ unsigned getRegBitWidth(unsigned RCID) {
case AMDGPU::AReg_256_Align2RegClassID:
case AMDGPU::AV_256RegClassID:
case AMDGPU::AV_256_Align2RegClassID:
case AMDGPU::SReg_256_XNULLRegClassID:
return 256;
case AMDGPU::SGPR_288RegClassID:
case AMDGPU::SReg_288RegClassID:
Expand Down
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