Chisel implementation of Neural Processing Unit for System on the Chip
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Oct 28, 2024 - Scala
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processor-design
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A basic implemention of 8 lane vector SIMD in RISC-V 5 Stage Pipeline, written in Chisel and Scala.
processor-architecture processor simd simd-parallelism risc-v processor-simulator processor-design risc-v-assembly risc-v-emulator
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Updated
Feb 23, 2025 - Scala
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