A small RISC-V core (SystemVerilog)
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Updated
Aug 26, 2019 - SystemVerilog
A small RISC-V core (SystemVerilog)
Superscalar dual-issue RISC-V processor
Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.
A System Verilog processor design of a single cycle MIPS architecture
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