riffpga -- write FPGA bitstreams through a USB drive, get USB serial and dynamic clocking in a platform independent way

上海交通大学软件学院🍭操作系统课程🍦实验

This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.

The published IEEE paper tells about the basic details of this project

FPGA programming for nanosecond photon counting

Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Cyclone V SoCFPGA

16 Bit Scientific Calculator Using Xilinx ISE 14.7 on Xilinx ISE, EDA Playground and Simple 4 bit calculator on Spartan 6 Board

implementing a protected communication platform between 2 FPGA's. Data is entered through a keyboard-FPGA interface then the data is encrypted using AES encryption and sent to the second FPGA where the decryption occurs if the decryption key is given and the data is displayed using an FPGA-LCD interface using VHDL scripts

FPGA Final Project

A project I made during my training, while learning VLSI. Used Verilog to program the FPGA board's 7 segment display to work as a counter, (configurable in up & down order).

This repository is primarily designed for my personal learning, featuring small projects and demonstration code based on ESP-32 and STM-32 platforms. Its main focus revolves around Real-Time Operating Systems (RTOS) and CPU architecture exploration.

XVC 1.0 daemon j-link support for Vivado

Mini SRC assembler for school project

Pong game with NES controller clones for the Digilent FPGA Dev Board Basys 3, coded in Verilog and C with IOb-SoC as base

FPGA-Based Digital Lock System with Digital Noise Filter

This personal project is a VHDL implementation of Bruce Schneier's blowfish algorithm which has seen no one break it till date. The algorithm uses a key with a multiple of 32 sizes, from 32 to 448. My implementation, however, does not have a specification on the multiple of 32 that the key size should be once it's between 32 and 448

Arithmetic Logic Unit in VHDL

C program that interacts with FPGA Board to validate Attendence requests based on Student Identifiers

FPGA solutions with Verilog hardware description language.

Pi Pico based SPI flash flasher