fix field pattern of CSR mstateen0 and hstateen0 in smstateen

[NewPaulWalker]

In newest Release riscv-isa-release-f3f8a93-2024-11-28 , the figures of mstateen0 and hstateen0 is incorrect, missing SE0 field.

[aswaterman]

Looks right to me, but cc @ved-rivos @bcstrongx.

[rock-ifly]

Anyone notice that mstateen0[55] is used by ssqosid extenstion, to control the access to srmcfg register

RISC-V Quality-of-Service (QoS) Identifiers (Ssqosid) Version v1.0, 2024-06-29: Ratified

If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the bit 55
in mstateen0 introduced by Priv 1.14 to be implemented. If bit 55 of mstateen0 is 0, attempts to access
srmcfg in privilege modes less privileged than M-mode raise an illegal-instruction exception. If bit
55 of mstateen0 is 1 or if extension Smstateen is not implemented, attempts to access srmcfg when
V=1 raise a virtual-instruction exception

[NewPaulWalker]

Anyone notice that mstateen0[55] is used by ssqosid extenstion, to control the access to srmcfg register

Yes, it is mentioned in the chapter about the Smstateen/Ssstateen extension in the Privileged Spec.

The P1P14 bit in mstateen0 controls access to the srmcfg CSR introduced by the Ssqosid Chapter 18 extension.

P1P14 corresponds to mstateen0[55].