Clarify CBO for unaligned rs1 #1433
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aswaterman
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May 29, 2024
ved-rivos
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Jul 5, 2024
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@ved-rivos @dkruckemyer-ventana any objection to merging this? I think the points Ved raised above are pre-existing issues (unless I've misunderstood) and therefore can be addressed in another PR. |
aswaterman
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Jul 26, 2024
aswaterman
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Jul 26, 2024
aswaterman
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Jul 26, 2024
aswaterman
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Jul 26, 2024
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I'm OK with it after the minor suggestions I made, but I still want @dkruckemyer-ventana to sign off.
Rework the text to be much more explicit about the behaviour when rs1 is not aligned to the cache block size. I also moved & slightly reworded the note about the assembly syntax since it's not relevant to the instruction semantics.
Timmmm
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Jan 6, 2025
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Jan 6, 2025
CBO faults report the address in rs1, not the cache block address. The spec is not explicit about this yet but I have a pending PR to clarify that: riscv/riscv-isa-manual#1433
Timmmm
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Jan 9, 2025
CBO faults report the address in rs1, not the cache block address. This has been clarified in the spec here: riscv/riscv-isa-manual#1433
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Rework the text to be much more explicit about the behaviour when rs1 is not aligned to the cache block size.
I also moved & slightly reworded the note about the assembly syntax since it's not relevant to the instruction semantics.
Fixes #1263