Allow BoringUtils to use existing port in a closed module (#4484)

* fix case ordering when drilling connection * add test
chipsalliance · Oct 25, 2024 · 9d58f0d · 9d58f0d
1 parent a7a68e5
commit 9d58f0d
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diff --git a/src/main/scala/chisel3/util/experimental/BoringUtils.scala b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
@@ -257,10 +257,10 @@ object BoringUtils {
     }
     def drill(source: A, path: Seq[BaseModule], connectionLocation: Seq[BaseModule], up: Boolean): A = {
       path.zip(connectionLocation).foldLeft(source) {
-        case (rhs, (module, conLoc)) if (module.isFullyClosed) => boringError(module); DontCare.asInstanceOf[A]
         case (rhs, (module, _)) if ((up || isDriveDone(rhs)) && module == path(0) && isPort(rhs)) => {
           rhs
         }
+        case (rhs, (module, conLoc)) if (module.isFullyClosed) => boringError(module); DontCare.asInstanceOf[A]
         case (rhs, (module, conLoc)) =>
           skipPrefix { // so `lcaSource` isn't in the name of the secret port
             if (!up && createProbe.nonEmpty && createProbe.get.writable) {

diff --git a/src/test/scala/chiselTests/BoringUtilsTapSpec.scala b/src/test/scala/chiselTests/BoringUtilsTapSpec.scala
@@ -922,4 +922,44 @@ class BoringUtilsTapSpec extends ChiselFlatSpec with ChiselRunners with Utils wi
     val e = the[ChiselException] thrownBy circt.stage.ChiselStage.emitCHIRRTL(new Top)
     e.getMessage should include("BoringUtils currently only support identity views")
   }
+
+  it should "reuse existing port in a closed module" in {
+    class Foo extends Module {
+      val io = IO(Output(UInt(32.W)))
+      val ioProbe = IO(probe.RWProbe(UInt(32.W)))
+      probe.define(ioProbe, probe.RWProbeValue(io))
+      io := 0.U
+    }
+
+    class Bar extends Module {
+      val foo = Module(new Foo)
+      val ioNames = reflect.DataMirror.modulePorts(foo).map(_._1) // close foo
+      val io = IO(Output(UInt(32.W)))
+      io := foo.io
+    }
+
+    class Baz extends Module {
+      val bar = Module(new Bar)
+      val reProbe = Wire(probe.RWProbe(UInt(32.W)))
+      probe.define(reProbe, BoringUtils.rwTap(bar.foo.ioProbe))
+      probe.forceInitial(reProbe, 1.U)
+    }
+
+    val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Baz)
+    matchesAndOmits(chirrtl)(
+      "module Foo :",
+      "output io : UInt<32>",
+      "output ioProbe : RWProbe<UInt<32>>",
+      "define ioProbe = rwprobe(io)",
+      "module Bar :",
+      "inst foo of Foo",
+      "output bore : RWProbe<UInt<32>>",
+      "define bore = foo.ioProbe",
+      "module Baz :",
+      "inst bar of Bar",
+      "wire reProbe : RWProbe<UInt<32>>",
+      "define reProbe = bar.bore",
+      "force_initial(reProbe, UInt<32>(0h1))"
+    )()
+  }
 }