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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.1k 611

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.3k 1.1k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.4k 219

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.1k 334

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 836 221

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 735 177

Repositories

Showing 10 of 110 repositories
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 9 Apache-2.0 5 14 5 Updated Jan 18, 2025
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 128 Apache-2.0 23 17 22 Updated Jan 17, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,094 Apache-2.0 611 313 (1 issue needs help) 172 Updated Jan 18, 2025
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 1 0 0 Updated Jan 18, 2025
  • firrtl-spec Public

    The specification for the FIRRTL language

    chipsalliance/firrtl-spec’s past year of commit activity
    TeX 49 28 25 17 Updated Jan 18, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 99 Apache-2.0 47 111 61 Updated Jan 18, 2025
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 79 Apache-2.0 44 78 11 Updated Jan 18, 2025
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge’s past year of commit activity
    SystemVerilog 13 Apache-2.0 2 6 1 Updated Jan 17, 2025
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 306 ISC 75 46 (5 issues need help) 33 Updated Jan 17, 2025
  • rocket-chip-inclusive-cache Public

    An RTL generator for a last-level shared inclusive TileLink cache controller

    chipsalliance/rocket-chip-inclusive-cache’s past year of commit activity
    Scala 15 Apache-2.0 20 6 4 Updated Jan 17, 2025
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