[Hexagon] Enable Hexagon User DMA bypass mode #13381
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janetsc
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Nov 15, 2022
| // VTCM -> VTCM | ||
| // NOTE: Cache bypass is disabled for VTCM -> VTCM transfers | ||
| ret = | ||
| user_dma->Copy(queue_id, vtcm2hb.GetPointer(), vtcm1hb.GetPointer(), length, DISABLE_BYPASS); |
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Since this is the enabled test, should it be ENABLE_BYPASS?
Edit - Ah, I see the comment. But you should be able to say ENABLED, and have it still work. It just won't actually enable anything. Or, should it through if you attempt to set bypass if it is vtcm to vtcm?
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User can "enable" or "disable" bypass and it will still work in all cases. Here is how the code operates:
- Sets bypass ON for VTCM -> DDR or DDR -> VTCM when the user enables bypass
- Sets bypass OFF for VTCM -> VTCM or DDR -> DDR regardless of whether the user enables bypass
Not sure if we should a) assert in case (2) when the user enables bypass or b) just silently turn bypass OFF. Currently I opt for (b) but I am open to feedback.
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Enables Hexagon User DMA bypass mode based on user-specified dma_bypass_cache option for DMA copies between DDR and VTCM. The upside of this change is increased DMA bandwidth (up to 40 GBps observed using test_vtcm_bandwidth.py) and compute throughput using a 3-stage pipeline --- cache read, compute, cache write (up to 38 Gops using test_parallel_hvx_load_vtcm.py). The downside of this change is the potential for data coherency issues resulting from the need to manage the cache in software when using DMA bypass hence the user dma_bypass_cache option to enable or disable bypass mode. The strategy to manage the cache in software centers around the requirement for Hexagon to operate on HexagonBuffer objects regardless of scope --- DDR or VTCM. When copying to / from a HexagonBuffer we aggressively invalidate the cache for both the source and destination, both before and after the copy. Also note that the copy is now implemented with memcpy instead of DMA. With the cache clean after copy to / from a HexagonBuffer we can now use DMA bypass mode. However, this software cache management strategy is NOT infallible --- if a HexagonBuffer becomes dirty in the cache prior to a DMA with bypass mode enabled we may see data coherency issues. Also simplifies Hexagon DMA flows by removing the unused mem_copy instrinsic and lowering as well as the hexagon_user_dma_1d_sync helper function which is replaced by calls to HexagonUserDMA::Copy and HexagonUserDMA::Wait. * restore vtcm tests; add TODO for ION buffer; check IsVtcm pointers
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Enables Hexagon User DMA bypass mode based on user-specified
dma_bypass_cacheoption for DMA copies between DDR and VTCM.The upside of this change is increased DMA bandwidth (up to 40 GBps observed using
test_vtcm_bandwidth.py) and compute throughput using a 3-stage pipeline --- cache read, compute, cache write (up to 38 Gops usingtest_parallel_hvx_load_vtcm.py).The downside of this change is the potential for data coherency issues resulting from the need to manage the cache in software when using DMA bypass hence the user
dma_bypass_cacheoption to enable or disable bypass mode.The strategy to manage the cache in software centers around the requirement for Hexagon to operate on
HexagonBufferobjects regardless of scope --- DDR or VTCM. When copying to / from aHexagonBufferwe aggressively invalidate the cache for both the source and destination, both before and after the copy. Also note that the copy is now implemented withmemcpyinstead of DMA. With the cache clean after copy to / from aHexagonBufferwe can now use DMA bypass mode. However, this software cache management strategy is NOT infallible --- if aHexagonBufferbecomes dirty in the cache prior to a DMA with bypass mode enabled we may see data coherency issues.Also simplifies Hexagon DMA flows by removing the unused
mem_copyinstrinsic and lowering as well as thehexagon_user_dma_1d_synchelper function which is replaced by calls toHexagonUserDMA::CopyandHexagonUserDMA::Wait.