[HEXAGON][QHL] Clippling the inputs of HVX version of QHL Sigmoid operation

[rahul-utkoor]

HVX version of QHL(Qualcomm Hexagon Library) sigmoid generates incorrect output if the input falls outside of [-8.0, 8.0]. To fix this, we need to clip the input to sigmoid in the range between >-8.0 and <8.0.

[masahi]

I believe we need to change

tvm/src/tir/op/op.cc

Line 869 in 397cf87

TIR_REGISTER_PURE_UNARY_OP("tir.sigmoid");

to enable sigmoid vectorization at the TIR level.

[masahi]

Can we check the generated asm to make sure that the HVX sigmoid is generated? It needs QHL to be enabled on Hexagon CI.

[rahul-utkoor]

I believe we need to change

tvm/src/tir/op/op.cc

Line 869 in 397cf87

TIR_REGISTER_PURE_UNARY_OP("tir.sigmoid");

to enable sigmoid vectorization at the TIR level.

@masahi
If we set attribute, TIR_REGISTER_PURE_UNARY_OP("tir.sigmoid").set_attr("TVectorizable", true);, the change will reflect when compiling for other targets as well. Can you tell me how do you want me handle this change? Or the current change is sufficient?

[masahi]

Good point, I don't find a way to make this per-target registration. For now I think it's fine to make sigmoid vectorizable, since looking at other ops this attribute is set somewhat arbitrarily. It should be easy to scalarize either TIR or LLVM level if necessary.