Skip to content

Commit

Permalink
Version 4.6
Browse files Browse the repository at this point in the history
  • Loading branch information
@ufrisk
ufrisk committed Jul 11, 2020
1 parent 00ab71d commit fc12780
Show file tree
Hide file tree
Showing 11 changed files with 143 additions and 29 deletions.
8 changes: 6 additions & 2 deletions NeTV2/src/pcileech_com.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ module pcileech_com (
output eth_led_state_green
`endif /* ENABLE_ETH */
);

// ----------------------------------------------------------------------------
// COMMUNICATION CORE INITIAL ON-BOARD DEFAULT RX-DATA
// Sometimes there is a need to perform actions - such as setting DRP-related
Expand Down Expand Up @@ -80,6 +80,10 @@ module pcileech_com (
time tickcount64 = 0;
always @ ( posedge clk )
tickcount64 <= rst ? 0 : tickcount64 + 1;

time tickcount64_com = 0;
always @ ( posedge clk_com )
tickcount64_com <= rst ? 0 : tickcount64_com + 1;

wire initial_rx_valid = ~rst & (tickcount64 >= 16) & (tickcount64 < $size(initial_rx) + 16);
wire [63:0] initial_rx_data = initial_rx_valid ? initial_rx[tickcount64 - 16] : 64'h0;
Expand Down Expand Up @@ -114,7 +118,7 @@ module pcileech_com (
end

fifo_64_64_clk2_comrx i_fifo_64_64_clk2_comrx(
.rst ( rst ),
.rst ( rst | (tickcount64_com<2) ),
.wr_clk ( clk_com ),
.rd_clk ( clk ),
.din ( com_rx_data64 ),
Expand Down
43 changes: 37 additions & 6 deletions NeTV2/src/pcileech_fifo.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,8 @@
`timescale 1ns / 1ps
`include "pcileech_header.svh"

//`define ENABLE_STARTUPE2

module pcileech_fifo #(
parameter PARAM_DEVICE_ID = 0,
parameter PARAM_VERSION_NUMBER_MAJOR = 0,
Expand Down Expand Up @@ -181,8 +183,9 @@ module pcileech_fifo #(
localparam RWPOS_WAIT_COMPLETE = 18; // WAIT FOR DRP COMPLETION
localparam RWPOS_DRP_RD_EN = 20;
localparam RWPOS_DRP_WR_EN = 21;
localparam RWPOS_GLOBAL_SYSTEM_RESET = 31;

wire [271:0] ro;
wire [279:0] ro;
reg [239:0] rw;

// special non-user accessible registers
Expand Down Expand Up @@ -216,7 +219,11 @@ module pcileech_fifo #(
assign ro[255:192] = _cmd_timer_inactivity_base; // +018: INACTIVITY TIMER
// PCIe DRP
assign ro[271:256] = rwi_drp_data; // +020: DRP: pcie_drp_do
// 0034
// PCIe
assign ro[272] = pcie_present; // +034: PCIe PRSNT#
assign ro[273] = pcie_perst_n; // PCIe PERST#
assign ro[279:274] = 0; // SLACK
// +035

// ------------------------------------------------------------------------
// INITIALIZATION/RESET BLOCK _AND_
Expand All @@ -236,7 +243,8 @@ module pcileech_fifo #(
rw[19] <= 0; // SLACK
rw[20] <= 0; // DRP RD EN
rw[21] <= 0; // DRP WR EN
rw[31:22] <= 0; // RESERVED FUTURE
rw[30:22] <= 0; // RESERVED FUTURE
rw[31] <= 0; // global system reset (GSR) via STARTUPE2 primitive
// SIZEOF / BYTECOUNT [little-endian]
rw[63:32] <= $bits(rw) >> 3; // +004: bytecount [little endian]
// CMD INACTIVITY TIMER TRIGGER VALUE
Expand All @@ -260,9 +268,7 @@ module pcileech_fifo #(
// PCIe DRP, PRSNT#, PERST#
rw[208+:16] <= 0; // +01A: DRP: pcie_drp_di
rw[224+:9] <= 0; // +01C: DRP: pcie_drp_addr
rw[233+:5] <= 0; // SLACK
rw[238] <= pcie_present; // PRSNT#
rw[239] <= pcie_perst_n; // PERST#
rw[233+:7] <= 0; // SLACK
// 01E -

end
Expand Down Expand Up @@ -390,4 +396,29 @@ module pcileech_fifo #(

end

// ----------------------------------------------------
// GLOBAL SYSTEM RESET: ( provided via STARTUPE2 primitive )
// ----------------------------------------------------
`ifdef ENABLE_STARTUPE2

STARTUPE2 #(
.PROG_USR ( "FALSE" ),
.SIM_CCLK_FREQ ( 0.0 )
) i_STARTUPE2 (
.CFGCLK ( ), // ->
.CFGMCLK ( ), // ->
.EOS ( ), // ->
.PREQ ( ), // ->
.CLK ( clk ), // <-
.GSR ( rw[RWPOS_GLOBAL_SYSTEM_RESET] ), // <- GLOBAL SYSTEM RESET
.GTS ( 1'b0 ), // <-
.KEYCLEARB ( 1'b0 ), // <-
.PACK ( 1'b0 ), // <-
.USRCCLKO ( 1'b0 ), // <-
.USRCCLKTS ( 1'b0 ), // <-
.USRDONEO ( 1'b1 ), // <-
.USRDONETS ( 1'b1 ) // <-
);
`endif /* ENABLE_STARTUPE2 */

endmodule
2 changes: 1 addition & 1 deletion NeTV2/src/pcileech_netv2_top.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ module pcileech_netv2_top #(
// 0 = SP605, 1 = PCIeScreamer R1, 2 = AC701, 3 = PCIeScreamer R2, 4 = Screamer M2, 5 = NeTV2
parameter PARAM_DEVICE_ID = 5,
parameter PARAM_VERSION_NUMBER_MAJOR = 4,
parameter PARAM_VERSION_NUMBER_MINOR = 5,
parameter PARAM_VERSION_NUMBER_MINOR = 6,
parameter PARAM_UDP_STATIC_ADDR = 32'hc0a800de, // 192.168.0.222
parameter PARAM_UDP_STATIC_FORCE = 1'b0,
parameter PARAM_UDP_PORT = 16'h6f3a // 28474
Expand Down
7 changes: 6 additions & 1 deletion ScreamerM2/readme.md
View file
Original file line number Diff line number Diff line change
Expand Up @@ -96,8 +96,13 @@ v4.4
* [ScreamerM2](https://mega.nz/file/VKhEjYwD#RZ_r90yVYB9UeCTdIaJZ1avTKVq4s25BBfWefgVOT0k) SHA256: `54ed5706357459d9595906b833155783801da9c1ef852c79e0533d4b613796df`

v4.5
* **PCILeech is free and open source. PCILeech is not directly affiliated with the NeTV2 and do not gain financially from sales. If you find PCILeech useful please consider supporting the project.**
* Fix for receiving initial data from PCILeech host.
* Download pre-built binaries below:
* [ScreamerM2](https://mega.nz/file/BSBVXKQI#2kD04ffpducrxojd4p2Iv9mr7ShHuScL5G8EU6xqn9w) SHA256: `04ca8e631981020dc12a4116c585e686def1b63d58660edb5970b00b3ce4592c`

v4.6
* **PCILeech is free and open source. PCILeech is not directly affiliated with the NeTV2 and do not gain financially from sales. If you find PCILeech useful please consider supporting the project.**
* Support connecting USB cable after device power-on.
* Download pre-built binaries below:
* [ScreamerM2](https://mega.nz/file/wbhn3BDA#vEpzHxNOSRsaEJXI4ce6OnPtjZECZVhIV4HEnRxV1T0) SHA256: `875c32a36934875f194af7d68648a5454c63aaa6ec4a730532632d9424148cd3`

8 changes: 6 additions & 2 deletions ScreamerM2/src/pcileech_com.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ module pcileech_com (
output eth_led_state_green
`endif /* ENABLE_ETH */
);

// ----------------------------------------------------------------------------
// COMMUNICATION CORE INITIAL ON-BOARD DEFAULT RX-DATA
// Sometimes there is a need to perform actions - such as setting DRP-related
Expand Down Expand Up @@ -80,6 +80,10 @@ module pcileech_com (
time tickcount64 = 0;
always @ ( posedge clk )
tickcount64 <= rst ? 0 : tickcount64 + 1;

time tickcount64_com = 0;
always @ ( posedge clk_com )
tickcount64_com <= rst ? 0 : tickcount64_com + 1;

wire initial_rx_valid = ~rst & (tickcount64 >= 16) & (tickcount64 < $size(initial_rx) + 16);
wire [63:0] initial_rx_data = initial_rx_valid ? initial_rx[tickcount64 - 16] : 64'h0;
Expand Down Expand Up @@ -114,7 +118,7 @@ module pcileech_com (
end

fifo_64_64_clk2_comrx i_fifo_64_64_clk2_comrx(
.rst ( rst ),
.rst ( rst | (tickcount64_com<2) ),
.wr_clk ( clk_com ),
.rd_clk ( clk ),
.din ( com_rx_data64 ),
Expand Down
43 changes: 37 additions & 6 deletions ScreamerM2/src/pcileech_fifo.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,8 @@
`timescale 1ns / 1ps
`include "pcileech_header.svh"

`define ENABLE_STARTUPE2

module pcileech_fifo #(
parameter PARAM_DEVICE_ID = 0,
parameter PARAM_VERSION_NUMBER_MAJOR = 0,
Expand Down Expand Up @@ -181,8 +183,9 @@ module pcileech_fifo #(
localparam RWPOS_WAIT_COMPLETE = 18; // WAIT FOR DRP COMPLETION
localparam RWPOS_DRP_RD_EN = 20;
localparam RWPOS_DRP_WR_EN = 21;
localparam RWPOS_GLOBAL_SYSTEM_RESET = 31;

wire [271:0] ro;
wire [279:0] ro;
reg [239:0] rw;

// special non-user accessible registers
Expand Down Expand Up @@ -216,7 +219,11 @@ module pcileech_fifo #(
assign ro[255:192] = _cmd_timer_inactivity_base; // +018: INACTIVITY TIMER
// PCIe DRP
assign ro[271:256] = rwi_drp_data; // +020: DRP: pcie_drp_do
// 0034
// PCIe
assign ro[272] = pcie_present; // +034: PCIe PRSNT#
assign ro[273] = pcie_perst_n; // PCIe PERST#
assign ro[279:274] = 0; // SLACK
// +035

// ------------------------------------------------------------------------
// INITIALIZATION/RESET BLOCK _AND_
Expand All @@ -236,7 +243,8 @@ module pcileech_fifo #(
rw[19] <= 0; // SLACK
rw[20] <= 0; // DRP RD EN
rw[21] <= 0; // DRP WR EN
rw[31:22] <= 0; // RESERVED FUTURE
rw[30:22] <= 0; // RESERVED FUTURE
rw[31] <= 0; // global system reset (GSR) via STARTUPE2 primitive
// SIZEOF / BYTECOUNT [little-endian]
rw[63:32] <= $bits(rw) >> 3; // +004: bytecount [little endian]
// CMD INACTIVITY TIMER TRIGGER VALUE
Expand All @@ -260,9 +268,7 @@ module pcileech_fifo #(
// PCIe DRP, PRSNT#, PERST#
rw[208+:16] <= 0; // +01A: DRP: pcie_drp_di
rw[224+:9] <= 0; // +01C: DRP: pcie_drp_addr
rw[233+:5] <= 0; // SLACK
rw[238] <= pcie_present; // PRSNT#
rw[239] <= pcie_perst_n; // PERST#
rw[233+:7] <= 0; // SLACK
// 01E -

end
Expand Down Expand Up @@ -390,4 +396,29 @@ module pcileech_fifo #(

end

// ----------------------------------------------------
// GLOBAL SYSTEM RESET: ( provided via STARTUPE2 primitive )
// ----------------------------------------------------
`ifdef ENABLE_STARTUPE2

STARTUPE2 #(
.PROG_USR ( "FALSE" ),
.SIM_CCLK_FREQ ( 0.0 )
) i_STARTUPE2 (
.CFGCLK ( ), // ->
.CFGMCLK ( ), // ->
.EOS ( ), // ->
.PREQ ( ), // ->
.CLK ( clk ), // <-
.GSR ( rw[RWPOS_GLOBAL_SYSTEM_RESET] ), // <- GLOBAL SYSTEM RESET
.GTS ( 1'b0 ), // <-
.KEYCLEARB ( 1'b0 ), // <-
.PACK ( 1'b0 ), // <-
.USRCCLKO ( 1'b0 ), // <-
.USRCCLKTS ( 1'b0 ), // <-
.USRDONEO ( 1'b1 ), // <-
.USRDONETS ( 1'b1 ) // <-
);
`endif /* ENABLE_STARTUPE2 */

endmodule
2 changes: 1 addition & 1 deletion ScreamerM2/src/pcileech_screamer_m2_top.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ module pcileech_screamer_m2_top #(
// 0 = SP605, 1 = PCIeScreamer R1, 2 = AC701, 3 = PCIeScreamer R2, 4 = Screamer M2, 5 = NeTV2
parameter PARAM_DEVICE_ID = 4,
parameter PARAM_VERSION_NUMBER_MAJOR = 4,
parameter PARAM_VERSION_NUMBER_MINOR = 5
parameter PARAM_VERSION_NUMBER_MINOR = 6
) (
// SYS
input clk,
Expand Down
4 changes: 4 additions & 0 deletions ac701_ft601/readme.md
View file
Original file line number Diff line number Diff line change
Expand Up @@ -71,3 +71,7 @@ v4.4
v4.5
* Fix for receiving initial data from PCILeech host.
* Download pre-built binary [here](https://mega.nz/file/8DIhlAgI#T-GBLdhtYj5pNSG0vIc2zhWr_3KmUZbFijS-cap23Hs). <br>SHA256: `fd1982b1e8e2da48b0fa75ffb196eb41ac45c13dbb25f7547bb084c4c152f4f7`

v4.6
* Support connecting USB cable after device power-on.
* Download pre-built binary [here](https://mega.nz/file/pfgHURoQ#IMx1m_JDmVGdEfesBU5M1qQ-Jmv3tGnFeFEXyXExp9c). <br>SHA256: `fdeb65b1580adeb9720cf10af9b67d72d092d024edb7096ff7f2f340c322c9c3`
4 changes: 2 additions & 2 deletions ac701_ft601/src/pcileech_ac701_top.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,10 @@

module pcileech_ac701_top #(
// DEVICE IDs as follows:
// 0 = SP605, 1 = PCIeScreamer R1, 2 = AC701, 3 = PCIeScreamer R2, 4 = PCIeScreamer M2, 5 = NeTV2
// 0 = SP605, 1 = PCIeScreamer R1, 2 = AC701, 3 = PCIeScreamer R2, 4 = Screamer M2, 5 = NeTV2
parameter PARAM_DEVICE_ID = 2,
parameter PARAM_VERSION_NUMBER_MAJOR = 4,
parameter PARAM_VERSION_NUMBER_MINOR = 5
parameter PARAM_VERSION_NUMBER_MINOR = 6
) (
// SYS
input sysclk_p,
Expand Down
8 changes: 6 additions & 2 deletions ac701_ft601/src/pcileech_com.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ module pcileech_com (
output eth_led_state_green
`endif /* ENABLE_ETH */
);

// ----------------------------------------------------------------------------
// COMMUNICATION CORE INITIAL ON-BOARD DEFAULT RX-DATA
// Sometimes there is a need to perform actions - such as setting DRP-related
Expand Down Expand Up @@ -80,6 +80,10 @@ module pcileech_com (
time tickcount64 = 0;
always @ ( posedge clk )
tickcount64 <= rst ? 0 : tickcount64 + 1;

time tickcount64_com = 0;
always @ ( posedge clk_com )
tickcount64_com <= rst ? 0 : tickcount64_com + 1;

wire initial_rx_valid = ~rst & (tickcount64 >= 16) & (tickcount64 < $size(initial_rx) + 16);
wire [63:0] initial_rx_data = initial_rx_valid ? initial_rx[tickcount64 - 16] : 64'h0;
Expand Down Expand Up @@ -114,7 +118,7 @@ module pcileech_com (
end

fifo_64_64_clk2_comrx i_fifo_64_64_clk2_comrx(
.rst ( rst ),
.rst ( rst | (tickcount64_com<2) ),
.wr_clk ( clk_com ),
.rd_clk ( clk ),
.din ( com_rx_data64 ),
Expand Down
43 changes: 37 additions & 6 deletions ac701_ft601/src/pcileech_fifo.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,8 @@
`timescale 1ns / 1ps
`include "pcileech_header.svh"

`define ENABLE_STARTUPE2

module pcileech_fifo #(
parameter PARAM_DEVICE_ID = 0,
parameter PARAM_VERSION_NUMBER_MAJOR = 0,
Expand Down Expand Up @@ -181,8 +183,9 @@ module pcileech_fifo #(
localparam RWPOS_WAIT_COMPLETE = 18; // WAIT FOR DRP COMPLETION
localparam RWPOS_DRP_RD_EN = 20;
localparam RWPOS_DRP_WR_EN = 21;
localparam RWPOS_GLOBAL_SYSTEM_RESET = 31;

wire [271:0] ro;
wire [279:0] ro;
reg [239:0] rw;

// special non-user accessible registers
Expand Down Expand Up @@ -216,7 +219,11 @@ module pcileech_fifo #(
assign ro[255:192] = _cmd_timer_inactivity_base; // +018: INACTIVITY TIMER
// PCIe DRP
assign ro[271:256] = rwi_drp_data; // +020: DRP: pcie_drp_do
// 0034
// PCIe
assign ro[272] = pcie_present; // +034: PCIe PRSNT#
assign ro[273] = pcie_perst_n; // PCIe PERST#
assign ro[279:274] = 0; // SLACK
// +035

// ------------------------------------------------------------------------
// INITIALIZATION/RESET BLOCK _AND_
Expand All @@ -236,7 +243,8 @@ module pcileech_fifo #(
rw[19] <= 0; // SLACK
rw[20] <= 0; // DRP RD EN
rw[21] <= 0; // DRP WR EN
rw[31:22] <= 0; // RESERVED FUTURE
rw[30:22] <= 0; // RESERVED FUTURE
rw[31] <= 0; // global system reset (GSR) via STARTUPE2 primitive
// SIZEOF / BYTECOUNT [little-endian]
rw[63:32] <= $bits(rw) >> 3; // +004: bytecount [little endian]
// CMD INACTIVITY TIMER TRIGGER VALUE
Expand All @@ -260,9 +268,7 @@ module pcileech_fifo #(
// PCIe DRP, PRSNT#, PERST#
rw[208+:16] <= 0; // +01A: DRP: pcie_drp_di
rw[224+:9] <= 0; // +01C: DRP: pcie_drp_addr
rw[233+:5] <= 0; // SLACK
rw[238] <= pcie_present; // PRSNT#
rw[239] <= pcie_perst_n; // PERST#
rw[233+:7] <= 0; // SLACK
// 01E -

end
Expand Down Expand Up @@ -390,4 +396,29 @@ module pcileech_fifo #(

end

// ----------------------------------------------------
// GLOBAL SYSTEM RESET: ( provided via STARTUPE2 primitive )
// ----------------------------------------------------
`ifdef ENABLE_STARTUPE2

STARTUPE2 #(
.PROG_USR ( "FALSE" ),
.SIM_CCLK_FREQ ( 0.0 )
) i_STARTUPE2 (
.CFGCLK ( ), // ->
.CFGMCLK ( ), // ->
.EOS ( ), // ->
.PREQ ( ), // ->
.CLK ( clk ), // <-
.GSR ( rw[RWPOS_GLOBAL_SYSTEM_RESET] ), // <- GLOBAL SYSTEM RESET
.GTS ( 1'b0 ), // <-
.KEYCLEARB ( 1'b0 ), // <-
.PACK ( 1'b0 ), // <-
.USRCCLKO ( 1'b0 ), // <-
.USRCCLKTS ( 1'b0 ), // <-
.USRDONEO ( 1'b1 ), // <-
.USRDONETS ( 1'b1 ) // <-
);
`endif /* ENABLE_STARTUPE2 */

endmodule

0 comments on commit fc12780

Please sign in to comment.