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Collection of leaked system prompts
A bare metal programming guide (ARM microcontrollers)
SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.
"Forked" from Xilinx/Edge-AI-Platform-Tutorials
shariethernet / DNNDK-YOLOv3
Forked from rulai-hu/DNNDK-YOLOv3"Forked" from Xilinx/Edge-AI-Platform-Tutorials
Convert darknet weights to caffemodel
A graphical processor simulator and assembly editor for the RISC-V ISA
An Arduino Library that facilitates packet-based serial communication using COBS or SLIP encoding.
4 stage, in-order, secure RISC-V core based on the CV32E40P
A curation of awesome portfolio website ideas for developers and designers to draw inspiration from. Raise a pull request to add more. 💜
Python on Zynq FPGA for Convolutional Neural Networks
eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
Using LC-3 Assembly, find the max value in an array.
This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSI…
Input files and commands needed for the workshop, sorted daywise
This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.
A list of resources related to the open-source FPGA projects
Bluespec environment for working with the ulx3s board and its lattice ecp5 fpga
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
An analytical cost model evaluating DNN mappings (dataflows and tiling).
MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)