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update Cargo.toml
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romancardenas committed Nov 20, 2023
1 parent 3d39bbf commit d7b4ae9
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7 changes: 4 additions & 3 deletions riscv-rt/Cargo.toml
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name = "riscv-rt"
version = "0.11.0"
rust-version = "1.59"
repository = "/~https://github.com/rust-embedded/riscv-rt"
repository = "/~https://github.com/rust-embedded/riscv"
authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
categories = ["embedded", "no-std"]
description = "Minimal runtime / startup for RISC-V CPU's"
documentation = "https://docs.rs/riscv-rt"
keywords = ["riscv", "runtime", "startup"]
license = "ISC"
edition = "2018"
edition = "2021"

[features]
s-mode = []
single-hart = []

[dependencies]
riscv = "0.10"
riscv = {path = "../riscv", version = "0.10"}
riscv-rt-macros = { path = "macros", version = "0.2.0" }

[dev-dependencies]
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1 change: 1 addition & 0 deletions riscv/Cargo.toml
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Expand Up @@ -7,6 +7,7 @@ repository = "/~https://github.com/rust-embedded/riscv"
authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
categories = ["embedded", "hardware-support", "no-std"]
description = "Low level access to RISC-V processors"
documentation = "https://docs.rs/riscv"
keywords = ["riscv", "register", "peripheral"]
license = "ISC"

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