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src/c-st-ext.adoc

@@ -271,8 +271,8 @@ encoding space for other instructions requiring fewer operand bits.
 
 To increase the reach of 16-bit instructions, data-transfer instructions
 use zero-extended immediates that are scaled by the size of the data in
-bytes: latexmath:[$\times$]4 for words, latexmath:[$\times$]8 for double
-words, and latexmath:[$\times$]16 for quad words.
+bytes: ×4 for words, ×8 for double
+words, and ×16 for quad words.
 
 RVC provides two variants of loads and stores. One uses the ABI stack
 pointer, 'x2', as the base address and can target any data register. The
@@ -283,77 +283,73 @@ registers.
 
 include::images/wavedrom/c-sp-load-store.adoc[]
 [c-sp-load-store]
-.Stack-Pointer-Based Loads and Stores--these instructions use the CI format.
-image::image_placeholder.png[]
-
+//.Stack-Pointer-Based Loads and Stores--these instructions use the CI format.
 
 These instructions use the CI format.
 
 C.LWSP loads a 32-bit value from memory into register _rd_. It computes
 an effective address by adding the _zero_-extended offset, scaled by 4,
-to the stack pointer, 'x2'. It expands to 'lw rd, offset(x2)''. C.LWSP is
-only valid when latexmath:[$\textit{rd}{\neq}\texttt{x0}$]; the code
-points with latexmath:[$\textit{rd}{=}\texttt{x0}$] are reserved.
+to the stack pointer, 'x2'. It expands to 'lw rd, offset(x2)'. C.LWSP is
+only valid when _rd_≠x0 the code
+points with _rd_=x0 are reserved.
 
 C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value
 from memory into register _rd_. It computes its effective address by
 adding the zero-extended offset, scaled by 8, to the stack pointer,
-'x2'. It expands to 'ld rd, offset(x2)''. C.LDSP is only valid when
-latexmath:[$\textit{rd}{\neq}\texttt{x0}$]; the code points with
-latexmath:[$\textit{rd}{=}\texttt{x0}$] are reserved.
+'x2'. It expands to 'ld rd, offset(x2)'. C.LDSP is only valid when
+_rd_≠x0 the code points with
+_rd_=x0 are reserved.
 
 C.LQSP is an RV128C-only instruction that loads a 128-bit value from
 memory into register _rd_. It computes its effective address by adding
 the zero-extended offset, scaled by 16, to the stack pointer, 'x2'. It
 expands to 'lq rd, offset(x2)'. C.LQSP is only valid when
-latexmath:[$\textit{rd}{\neq}\texttt{x0}$]; the code points with
-latexmath:[$\textit{rd}{=}\texttt{x0}$] are reserved.
+_rd_&#x2260x0 the code points with
+_rd_=x0 are reserved.
 
 C.FLWSP is an RV32FC-only instruction that loads a single-precision
 floating-point value from memory into floating-point register _rd_. It
 computes its effective address by adding the _zero_-extended offset,
-scaled by 4, to the stack pointer, `x2`. It expands to
-`flw rd, offset(x2)`.
+scaled by 4, to the stack pointer, 'x2'. It expands to
+'flw rd, offset(x2)'.
 
 C.FLDSP is an RV32DC/RV64DC-only instruction that loads a
 double-precision floating-point value from memory into floating-point
 register _rd_. It computes its effective address by adding the
-_zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It
-expands to `fld rd, offset(x2)`.
+_zero_-extended offset, scaled by 8, to the stack pointer, 'x2'. It
+expands to 'fld rd, offset(x2)'.
 
 include::images/wavedrom/c-sp-load-store-css.adoc[]
 [c-sp-load-store-css]
-.Stack-Pointer-Based Loads and Stores--these instructions use the CSS format.
-
-image::image_placeholder.png[]
+//.Stack-Pointer-Based Loads and Stores--these instructions use the CSS format.
 
 These instructions use the CSS format.
 
 C.SWSP stores a 32-bit value in register _rs2_ to memory. It computes an
 effective address by adding the _zero_-extended offset, scaled by 4, to
-the stack pointer, `x2`. It expands to `sw rs2, offset(x2)`.
+the stack pointer, 'x2'. It expands to 'sw rs2, offset(x2)'.
 
 C.SDSP is an RV64C/RV128C-only instruction that stores a 64-bit value in
 register _rs2_ to memory. It computes an effective address by adding the
-_zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It
-expands to `sd rs2, offset(x2)`.
+_zero_-extended offset, scaled by 8, to the stack pointer, 'x2'. It
+expands to 'sd rs2, offset(x2)''.
 
 C.SQSP is an RV128C-only instruction that stores a 128-bit value in
 register _rs2_ to memory. It computes an effective address by adding the
-_zero_-extended offset, scaled by 16, to the stack pointer, `x2`. It
-expands to `sq rs2, offset(x2)`.
+_zero_-extended offset, scaled by 16, to the stack pointer, 'x2'. It
+expands to sq rs2, offset(x2)'.
 
 C.FSWSP is an RV32FC-only instruction that stores a single-precision
 floating-point value in floating-point register _rs2_ to memory. It
 computes an effective address by adding the _zero_-extended offset,
-scaled by 4, to the stack pointer, `x2`. It expands to
-`fsw rs2, offset(x2)`.
+scaled by 4, to the stack pointer, 'x2'. It expands to
+'fsw rs2, offset(x2)'.
 
 C.FSDSP is an RV32DC/RV64DC-only instruction that stores a
 double-precision floating-point value in floating-point register _rs2_
 to memory. It computes an effective address by adding the
 _zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It
-expands to `fsd rs2, offset(x2)`.
+expands to 'fsd rs2, offset(x2)'.
 
 [NOTE]
 ====
@@ -387,7 +383,7 @@ featured registers selected for the CIW, CL, CS, CA, and CB formats.
 
 Furthermore, much of the gains can be realized in software by replacing
 prologue and epilogue code with subroutine calls to common prologue and
-epilogue code, a technique described in Section 5.6 of .
+epilogue code, a technique described in Section 5.6 of [ADD CITE HERE].
 
 While reasonable architects might come to different conclusions, we
 decided to omit load and store multiple and instead use the
@@ -399,17 +395,16 @@ attain the greatest code size reduction.
 
 [[reg-based-ldnstr]]
 include::images/wavedrom/reg-based-ldnstr.adoc[]
-.Compressed, register-based load and stores--these instructions use the CL format.
-image::image_placeholder.png[]
+//.Compressed, register-based load and stores--these instructions use the CL format.
 (((compressed, register-based load and store)))
 
 These instructions use the CL format.
 
 C.LW loads a 32-bit value from memory into register
-_rd latexmath:[$'$]_. It computes an effective address by adding the
+_rd′_. It computes an effective address by adding the
 _zero_-extended offset, scaled by 4, to the base address in register
-_rs1 latexmath:[$'$]_. It expands to
-`lw rd `latexmath:[$'$]`, offset(rs1 `latexmath:[$'$]`)`.
+_rs1′_. It expands to
+`lw rd′`, `offset(rs1′)`.
 
 C.LD is an RV64C/RV128C-only instruction that loads a 64-bit value from
 memory into register _rd latexmath:[$'$]_. It computes an effective