Merge pull request #42 from ppisa/main

CTU Computer Architectures course correct university link and add QtRvSim online links

README.md

@@ -68,7 +68,7 @@ For those with little or no knowledge of digital logic design. After studying th
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 |  <span id="digital-design">**Digital Design and Computer Architecture RISC-V edition**</span> (good starting point) | Sarah L. Harris, David M. Harris   | Covers the foundational knowledge of digital logic design and segues smoothly into RISC-V Processor implementation. <i><br><br><ins>Topics</ins>: Number systems and digital representation, Semiconductors and transistors, Logic gates and Digital design, C Programming, RISC-V architecture, RISC-V assembly, Memory systems, Embedded I/O systems</i> | <a href="https://www.amazon.com/Digital-Design-Computer-Architecture-RISC-V/dp/0128200642/ref=sr_1_5?crid=1Y6VGCXHTB99I&keywords=digital+design+and+computer+architecture&qid=1659609065&sprefix=digital+design+and+computer+architecture%2Caps%2C135&sr=8-5" target="_blank">[Amazon book link]</a>| 2024-01-10 |
 |  <span id="digital-design">**The RISC-V Reader: An Open Architecture Atlas**</span> | David Patterson, Andrew Waterman| A beginner-friendly introduction to the RISC-V instruction set architecture as readers can start programming after the 2nd chapter. <i><br><br><ins>Topics</ins>: Computer architecture, RISC-V Instruction Set Architecture (ISA)</i> | <a href="http://www.riscbook.com/" target="_blank">[Available in Chineses, Japanese, Spanish, Portuguese and Korean]</a>| 2024-03-05 |
-|**Computer Architecture Basics** | [CTU Prague](https://cw.fel.cvut.cz/wiki/start) | This course introduces the fundamentals of computer architecture, covering topics such as binary number representation, CPU design, memory hierarchy, pipelined execution, and speculative execution techniques.<i><br><br><ins>Topics</ins>: Computer architecture<br></i>|<a href="https://cw.fel.cvut.cz/wiki/courses/b35apo/en/lectures/start" target="_blank"> [Online course videos]| 2024-04-16 |
+|**Computer Architecture Basics** | [CTU Prague - FEE](https://fel.cvut.cz/en) (Pavel Pisa) | This course introduces the fundamentals of computer architecture, covering topics such as binary number representation, CPU design, memory hierarchy, pipelined execution, and speculative execution techniques. It is paired with  <a href="https://comparch.edu.cvut.cz/" target="_blank">QtRvSim</a> for demonstrations.<i><br><br><ins>Topics</ins>: Computer architecture<br></i>|<a href="https://cw.fel.cvut.cz/wiki/courses/b35apo/en/lectures/start" target="_blank"> [Online course videos]| 2024-04-16 |
 | **Nand2Tetris** (optional) | Noam Nisan, Shimon Schocken | A free hands-on tutorial on building a general-purpose computer from logic gates using a hardware simulator. <i><br><br><ins>Topics</ins>: Logic gates<i>|<a href="https://www.nand2tetris.org/" target="_blank">[webpage]</a> | 2024-01-10 |
 |<span id="bruno-levy-episode-1">**learn-FPGA episode I: from blinky to RISC-V**</span>|[BrunoLevy](/~https://github.com/BrunoLevy)|A beginner's introduction to the digital design of a RISC-V softcore on FPGAs. Episode I gently starts from a very basic blinker in Verilog and morphs it step by step into a basic yet fully functional RISC-V SoC. It also explains how to write programs in C and assembly for the SoC.<i><br><br><ins>Topics</ins>: Digital design, FPGA, C Programming, RISC-V assembly<br><ins>Requirement</ins>: Basic knowledge of Verilog</i>|<a href="/~https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/README.md" target="_blank">[GitHub]</a>| 2024-01-10 |
 |**Hands-on RISC-V Processor Design**|[Rahul Behl](/~https://github.com/raulbehl)|This practical tutorial offers a deep dive into the world of computer architecture and processor design, with a specific focus on the RISC-V Instruction Set Architecture (ISA).<i><br><br><ins>Topics</ins>: Computer architecture, Processor design, RISC-V Instruction Set Architecture (ISA), SystemVerilog, RISC-V assembly<br><ins>Requirements</ins>: SystemVerilog but not necessary</i>|<a href="https://quicksilicon.in/course/riscv" target="_blank">[webpage]</a> | 2024-01-10 |
@@ -108,7 +108,7 @@ A collection of tools that can be used along with the beginner or intermediate-l
 | **emulsiV** | Guillaume Savaton, ESEO | emulsiV is a visual simulator for a simple RISC processor called Virgule. Virgule is a 32-bit RISC processor core that implements a minimal subset of the RISC-V instruction set. Here, “minimal” means that Virgule accepts only the instructions that a C compiler would generate from a pure stand-alone C program. | <a href="https://eseo-tech.github.io/emulsiV/" target="_blank">[website]</a> | 2023-20-12 |
 | **RISC-V Instruction Encoder/Decoder** | LupLab @ University of California, Davis | This tool is an online encoder/decoder for RISC-V instructions. Users can input RISC-V instructions in their assembly or binary format and get the full conversion from one to the other. | <a href="https://luplab.gitlab.io/rvcodecjs/" target="_blank">[website]</a> | 2023-20-12 |
 | **CREATOR** | Diego Camarmas Alonso,Félix García Carballeira,Alejandro Calderón Mateos,Elías del Pozo Puñal | CREATOR is a didactic simulator that allows the development, simulation, and debugging of RISC-V (RV32IMFD) assembly programs intuitively and interactively. It is a web application, so it can be used on any type of device (desktop, tablet, smartphone, etc.) without installing additional software. Only a modern web browser (Google Chrome, Mozilla Firefox, Apple Safari, etc.) is required. | <a href="https://creatorsim.github.io/creator/" target="_blank">[website]</a> | 2023-20-12 |
-| **QtRvSim** - RISC-V CPU Simulator with Cache and Pipeline Visualization | Computer Architectures Education project at Czech Technical University | QtRvSim is educational simulator with pipeline and cache visualization (RV32IMA/RV64IMA). It supports even M-mode ecalls, ACLINT MTIMER, MSWI, SSWI, related CSR registers, serial port Rx and Tx interrupts and more. | <a href="/~https://github.com/cvut/qtrvsim/" target="_blank">[Github]</a> | 2023-20-12 |
+| **QtRvSim** - RISC-V CPU Simulator with Cache and Pipeline Visualization | <a href="https://comparch.edu.cvut.cz/" target="_blank">Computer Architectures Education</a> team at <a href="https://www.cvut.cz/en" target="_blank">Czech Technical University</a> | QtRvSim is educational simulator with pipeline and cache visualization (RV32IMA/RV64IMA). It supports even M-mode ecalls, ACLINT MTIMER, MSWI, SSWI, related CSR registers, serial port Rx and Tx interrupts and more. | <a href="/~https://github.com/cvut/qtrvsim/" target="_blank">[Github]</a> and <a href="https://comparch.edu.cvut.cz/qtrvsim/app" target="_blank">[Online]</a> | 2023-20-12 |
 | **RVV intrinsics viewer** | dzaima | A third party documentation website for the vector extension intrinsics, currently including pretty much all intrinsics variations, and fuzzy search. This can be a useful resource when writing rvv code. | <a href="https://dzaima.github.io/intrinsics-viewer/" target="_blank">[website]</a> | 2023-20-12 |
 
 #### Open RISC-V Implementations