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RISC-V Debug Support v0.1
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@bluewww bluewww released this 24 May 16:40
· 194 commits to master since this release
v0.1
6d768ac
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Learn about vigilant mode.

Added

  • Parametrize buswidth to support 32-bit and 64-bit cores
  • Support arbitrary base addresses in debug ROM
  • Add misc helper functions to facilitate code generation
  • Add README
  • Fork from Ariane

Changed

  • Allow generic number of data registers
  • Make JTAG IDCODE parametrizable

Removed

  • Remove ariane specific packages

Fixed

  • Fix resumeack and resumereq behaviour to be cleared and set according to debug
    specification
  • Add missing JTAG test logic reset handling
  • Fix resume logic in multihart situations
  • Fix missing else(s) in system bus access
  • Fix bad transitions into program buffer
  • Fix error handling when using unsupported abstract commands
  • Prevent harts from being in multiple states
  • Fix various style issues
Assets 2
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