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Merge pull request #25 from NilsGraf/dbg1
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Lint clean ups
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bluewww authored Jul 19, 2019
2 parents 6d768ac + b4aa4f2 commit d4e9155
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Showing 3 changed files with 18 additions and 11 deletions.
25 changes: 16 additions & 9 deletions src/dm_csrs.sv
Original file line number Diff line number Diff line change
Expand Up @@ -93,16 +93,22 @@ module dm_csrs #(
localparam dm::dm_csr_e ProgBufEnd = dm::dm_csr_e'((dm::ProgBuf0 + {4'b0, dm::ProgBufSize}));

logic [31:0] haltsum0, haltsum1, haltsum2, haltsum3;
logic [NrHarts/2**5 :0][31:0] halted_reshaped0;
logic [((NrHarts-1)/2**5 + 1) * 32 - 1 : 0] halted;
logic [(NrHarts-1)/2**5:0][31:0] halted_reshaped0;
logic [NrHarts/2**10:0][31:0] halted_reshaped1;
logic [NrHarts/2**15:0][31:0] halted_reshaped2;
logic [(NrHarts/2**10+1)*32-1:0] halted_flat1;
logic [(NrHarts/2**15+1)*32-1:0] halted_flat2;
logic [32-1:0] halted_flat3;

// haltsum0
assign halted_reshaped0 = halted_i;
assign haltsum0 = halted_reshaped0[hartsel_o[19:5]];
always_comb begin
halted = '0;
halted[NrHarts-1:0] = halted_i;
halted_reshaped0 = halted;
haltsum0 = halted_reshaped0[hartsel_o[19:5]];
end

// haltsum1
always_comb begin : p_reduction1
halted_flat1 = '0;
Expand Down Expand Up @@ -188,8 +194,8 @@ module dm_csrs #(

// as soon as we are out of the legal Hart region tell the debugger
// that there are only non-existent harts
dmstatus.allnonexistent = (hartsel_o > (NrHarts[19:0] - 1)) ? 1'b1 : 1'b0;
dmstatus.anynonexistent = (hartsel_o > (NrHarts[19:0] - 1)) ? 1'b1 : 1'b0;
dmstatus.allnonexistent = (hartsel_o > (NrHarts - 1)) ? 1'b1 : 1'b0;
dmstatus.anynonexistent = (hartsel_o > (NrHarts - 1)) ? 1'b1 : 1'b0;

// We are not allowed to be in multiple states at once. This is a to
// make the running/halted and unavailable states exclusive.
Expand Down Expand Up @@ -354,8 +360,8 @@ module dm_csrs #(
// this field can only be written legally when there is no command executing
if (!cmdbusy_i) begin
abstractauto_d = 32'b0;
abstractauto_d.autoexecdata = dmi_req_i.data[dm::DataCount-1:0];
abstractauto_d.autoexecprogbuf = dmi_req_i.data[dm::ProgBufSize-1+16:16];
abstractauto_d.autoexecdata = 12'(dmi_req_i.data[dm::DataCount-1:0]);
abstractauto_d.autoexecprogbuf = 16'(dmi_req_i.data[dm::ProgBufSize-1+16:16]);

end else if (cmderr_q == dm::CmdErrNone) begin
cmderr_d = dm::CmdErrBusy;
Expand All @@ -378,7 +384,8 @@ module dm_csrs #(
if (sbbusy_i) begin
sbcs_d.sbbusyerror = 1'b1;
end else begin
automatic dm::sbcs_t sbcs = dm::sbcs_t'(dmi_req_i.data);
automatic dm::sbcs_t sbcs;
sbcs = dm::sbcs_t'(dmi_req_i.data);
sbcs_d = sbcs;
// R/W1C
sbcs_d.sbbusyerror = sbcs_q.sbbusyerror & (~sbcs.sbbusyerror);
Expand Down Expand Up @@ -444,7 +451,7 @@ module dm_csrs #(
end
// update read data
if (sbdata_valid_i) begin
sbdata_d = sbdata_i;
sbdata_d = 64'(sbdata_i);
end

// dmcontrol
Expand Down
2 changes: 1 addition & 1 deletion src/dm_mem.sv
Original file line number Diff line number Diff line change
Expand Up @@ -428,7 +428,7 @@ module dm_mem #(
end

logic [63:0] rom_addr;
assign rom_addr = addr_i;
assign rom_addr = 64'(addr_i);
debug_rom i_debug_rom (
.clk_i,
.req_i,
Expand Down
2 changes: 1 addition & 1 deletion src/dmi_jtag.sv
Original file line number Diff line number Diff line change
Expand Up @@ -137,7 +137,7 @@ module dmi_jtag #(
end
end

WaitWriteValid: begin
default: begin
// just wait for idle here
if (dmi_resp_valid) begin
state_d = Idle;
Expand Down

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