odly wire added

os-fpga · Dec 3, 2024 · b28ee96 · b28ee96
1 parent 08db226
commit b28ee96
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/rapidsilicon/ip/io_configurator/v1_0/src/DLY_CONFIG.v b/rapidsilicon/ip/io_configurator/v1_0/src/DLY_CONFIG.v
@@ -400,6 +400,7 @@ end
 
 `ifdef bidirectional
 wire  [(NUM_DLY/2)-1:0] i_buf_out;
+wire  [(NUM_DLY/2)-1:0] odly_out;
 
 generate
     for(genvar i = 0; i < NUM_DLY/2; i = i + 1) begin