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[LoongArch] lower SCALAR_TO_VECTOR to INSERT_VECTOR_ELT #122863

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merged 8 commits into from
Jan 22, 2025
Merged

[LoongArch] lower SCALAR_TO_VECTOR to INSERT_VECTOR_ELT #122863

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7e36c8d
lower SCALAR_TO_VECTOR to INSERT_VECTOR_ELT
tangaac Jan 14, 2025
d574316
lower SCALAR_TO_VECTOR to INSERT_VECTOR_ELT
tangaac Jan 14, 2025
6d36284
Merge branch 'scalar-to-vector' of github.com:tangaac/llvm-project in…
tangaac Jan 14, 2025
deae039
minor changes
tangaac Jan 16, 2025
4bba81b
replace undef with poison
tangaac Jan 16, 2025
5cf9af0
simplify scalar_to_vector for float vector types
tangaac Jan 17, 2025
a71a98f
Update llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
tangaac Jan 20, 2025
948416e
Update llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
tangaac Jan 20, 2025
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6 changes: 4 additions & 2 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -255,7 +255,6 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SETCC, VT, Legal);
setOperationAction(ISD::VSELECT, VT, Legal);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
}
for (MVT VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) {
setOperationAction({ISD::ADD, ISD::SUB}, VT, Legal);
Expand All @@ -270,6 +269,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setCondCodeAction(
{ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT,
Expand);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
}
for (MVT VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
setOperationAction(ISD::BITREVERSE, VT, Custom);
Expand All @@ -288,6 +288,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT,
ISD::SETUGE, ISD::SETUGT},
VT, Expand);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
}
setOperationAction(ISD::CTPOP, GRLenVT, Legal);
setOperationAction(ISD::FCEIL, {MVT::f32, MVT::f64}, Legal);
Expand All @@ -312,7 +313,6 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SETCC, VT, Legal);
setOperationAction(ISD::VSELECT, VT, Legal);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
}
for (MVT VT : {MVT::v4i64, MVT::v8i32, MVT::v16i16, MVT::v32i8}) {
setOperationAction({ISD::ADD, ISD::SUB}, VT, Legal);
Expand All @@ -327,6 +327,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setCondCodeAction(
{ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT,
Expand);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
}
for (MVT VT : {MVT::v32i8, MVT::v16i16, MVT::v8i32})
setOperationAction(ISD::BITREVERSE, VT, Custom);
Expand All @@ -345,6 +346,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT,
ISD::SETUGE, ISD::SETUGT},
VT, Expand);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
}
}

Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
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Expand Up @@ -1562,6 +1562,12 @@ def : Pat<(vector_insert v8f32:$vd, FPR32:$fj, uimm3:$imm),
def : Pat<(vector_insert v4f64:$vd, FPR64:$fj, uimm2:$imm),
(XVINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm2:$imm)>;

// scalar_to_vector
def : Pat<(v8f32 (scalar_to_vector FPR32:$fj)),
(SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32)>;
def : Pat<(v4f64 (scalar_to_vector FPR64:$fj)),
(SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64)>;
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// XVPICKVE2GR_W[U]
def : Pat<(loongarch_vpick_sext_elt v8i32:$xd, uimm3:$imm, i32),
(XVPICKVE2GR_W v8i32:$xd, uimm3:$imm)>;
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
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Expand Up @@ -1719,6 +1719,12 @@ def : Pat<(vector_insert v4f32:$vd, FPR32:$fj, uimm2:$imm),
def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, uimm1:$imm),
(VINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm1:$imm)>;

// scalar_to_vector
def : Pat<(v4f32 (scalar_to_vector FPR32:$fj)),
(SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32)>;
def : Pat<(v2f64 (scalar_to_vector FPR64:$fj)),
(SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64)>;
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// VPICKVE2GR_{B/H/W}[U]
def : Pat<(loongarch_vpick_sext_elt v16i8:$vd, uimm4:$imm, i8),
(VPICKVE2GR_B v16i8:$vd, uimm4:$imm)>;
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
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Expand Up @@ -42,8 +42,7 @@ define <4 x i64> @scalar_to_4xi64(i64 %val) {
define <8 x float> @scalar_to_8xf32(float %val) {
; CHECK-LABEL: scalar_to_8xf32:
; CHECK: # %bb.0:
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 0
; CHECK-NEXT: # kill: def $f0 killed $f0 def $xr0
; CHECK-NEXT: ret
%ret = insertelement <8 x float> poison, float %val, i32 0
ret <8 x float> %ret
Expand All @@ -52,8 +51,7 @@ define <8 x float> @scalar_to_8xf32(float %val) {
define <4 x double> @scalar_to_4xf64(double %val) {
; CHECK-LABEL: scalar_to_4xf64:
; CHECK: # %bb.0:
; CHECK-NEXT: movfr2gr.d $a0, $fa0
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 0
; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $xr0
; CHECK-NEXT: ret
%ret = insertelement <4 x double> poison, double %val, i32 0
ret <4 x double> %ret
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll
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Expand Up @@ -42,8 +42,7 @@ define <2 x i64> @scalar_to_2xi64(i64 %val) {
define <4 x float> @scalar_to_4xf32(float %val) {
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Seems these could be empty because FR overlap with the lower part of the SIMD register.

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vector_insert in .td files cannot deal with this.
We could make v4f32, v2f64 Legal, and process scalar_to_vector in .td files like this,

def : Pat<(v4f32 (scalar_to_vector FPR32:$fj)),
          (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32)>;
def : Pat<(v2f64 (scalar_to_vector FPR64:$fj)),
          (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64)>;

; CHECK-LABEL: scalar_to_4xf32:
; CHECK: # %bb.0:
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0
; CHECK-NEXT: ret
%ret = insertelement <4 x float> poison, float %val, i32 0
ret <4 x float> %ret
Expand All @@ -52,8 +51,7 @@ define <4 x float> @scalar_to_4xf32(float %val) {
define <2 x double> @scalar_to_2xf64(double %val) {
; CHECK-LABEL: scalar_to_2xf64:
; CHECK: # %bb.0:
; CHECK-NEXT: movfr2gr.d $a0, $fa0
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0
; CHECK-NEXT: ret
%ret = insertelement <2 x double> poison, double %val, i32 0
ret <2 x double> %ret
Expand Down
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