Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[AMDGPU] Disallow null for more resource operands #121941

Merged
merged 1 commit into from
Jan 8, 2025
+52 −12
Merged

[AMDGPU] Disallow null for more resource operands #121941

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/BUFInstructions.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -680,7 +680,7 @@ multiclass MUBUF_Pseudo_Stores<string opName, ValueType store_vt = i32> {
class MUBUF_Pseudo_Store_Lds<string opName>
: MUBUF_Pseudo<opName,
(outs),
(ins SReg_128:$srsrc, SCSrc_b32:$soffset, Offset:$offset, CPol:$cpol, i1imm:$swz),
(ins SReg_128_XNULL:$srsrc, SCSrc_b32:$soffset, Offset:$offset, CPol:$cpol, i1imm:$swz),
Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This change is just for consistency. It doesn't make a practical difference because this instruction only exists pre-GFX10, but "null" only exists in GFX10+.

" $srsrc, $soffset$offset lds$cpol"> {
let LGKM_CNT = 1;
let mayLoad = 1;
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/AMDGPU/MIMGInstructions.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1524,21 +1524,21 @@ class MIMG_IntersectRay_Helper<bit Is64, bit IsA16> {

class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC>
: MIMG_gfx10<op.GFX10M, (outs VReg_128:$vdata), "GFX10"> {
let InOperandList = (ins AddrRC:$vaddr0, SReg_128:$srsrc, A16:$a16);
let InOperandList = (ins AddrRC:$vaddr0, SReg_128_XNULL:$srsrc, A16:$a16);
let AsmString = opcode#" $vdata, $vaddr0, $srsrc$a16";

let nsa = 0;
}

class MIMG_IntersectRay_nsa_gfx10<mimgopc op, string opcode, int num_addrs>
: MIMG_nsa_gfx10<op.GFX10M, (outs VReg_128:$vdata), num_addrs, "GFX10"> {
let InOperandList = !con(nsah.AddrIns, (ins SReg_128:$srsrc, A16:$a16));
let InOperandList = !con(nsah.AddrIns, (ins SReg_128_XNULL:$srsrc, A16:$a16));
let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc$a16";
}

class MIMG_IntersectRay_gfx11<mimgopc op, string opcode, RegisterClass AddrRC>
: MIMG_gfx11<op.GFX11, (outs VReg_128:$vdata), "GFX11"> {
let InOperandList = (ins AddrRC:$vaddr0, SReg_128:$srsrc, A16:$a16);
let InOperandList = (ins AddrRC:$vaddr0, SReg_128_XNULL:$srsrc, A16:$a16);
let AsmString = opcode#" $vdata, $vaddr0, $srsrc$a16";

let nsa = 0;
Expand All @@ -1548,15 +1548,15 @@ class MIMG_IntersectRay_nsa_gfx11<mimgopc op, string opcode, int num_addrs,
list<RegisterClass> addr_types>
: MIMG_nsa_gfx11<op.GFX11, (outs VReg_128:$vdata), num_addrs, "GFX11",
addr_types> {
let InOperandList = !con(nsah.AddrIns, (ins SReg_128:$srsrc, A16:$a16));
let InOperandList = !con(nsah.AddrIns, (ins SReg_128_XNULL:$srsrc, A16:$a16));
let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc$a16";
}

class VIMAGE_IntersectRay_gfx12<mimgopc op, string opcode, int num_addrs,
list<RegisterClass> addr_types>
: VIMAGE_gfx12<op.GFX12, (outs VReg_128:$vdata),
num_addrs, "GFX12", addr_types> {
let InOperandList = !con(nsah.AddrIns, (ins SReg_128:$rsrc, A16:$a16));
let InOperandList = !con(nsah.AddrIns, (ins SReg_128_XNULL:$rsrc, A16:$a16));
let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $rsrc$a16";
}

Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/AMDGPU/SMInstructions.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -341,10 +341,10 @@ let SubtargetPredicate = HasScalarDwordx3Loads in
defm S_BUFFER_LOAD_DWORDX4 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_128>;
defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_256>;
defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_512>;
defm S_BUFFER_LOAD_I8 : SM_Pseudo_Loads <SReg_128, SReg_32_XM0_XEXEC>;
defm S_BUFFER_LOAD_U8 : SM_Pseudo_Loads <SReg_128, SReg_32_XM0_XEXEC>;
defm S_BUFFER_LOAD_I16 : SM_Pseudo_Loads <SReg_128, SReg_32_XM0_XEXEC>;
defm S_BUFFER_LOAD_U16 : SM_Pseudo_Loads <SReg_128, SReg_32_XM0_XEXEC>;
defm S_BUFFER_LOAD_I8 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_32_XM0_XEXEC>;
defm S_BUFFER_LOAD_U8 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_32_XM0_XEXEC>;
defm S_BUFFER_LOAD_I16 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_32_XM0_XEXEC>;
defm S_BUFFER_LOAD_U16 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_32_XM0_XEXEC>;
}

let SubtargetPredicate = HasScalarStores in {
Expand Down Expand Up @@ -375,7 +375,7 @@ def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb

defm S_ATC_PROBE : SM_Pseudo_Probe <SReg_64>;
let is_buffer = 1 in {
defm S_ATC_PROBE_BUFFER : SM_Pseudo_Probe <SReg_128>;
defm S_ATC_PROBE_BUFFER : SM_Pseudo_Probe <SReg_128_XNULL>;
}
} // SubtargetPredicate = isGFX8Plus

Expand Down Expand Up @@ -470,7 +470,7 @@ def S_PREFETCH_INST : SM_Prefetch_Pseudo <"s_prefetch_inst", SReg_64, 1>;
def S_PREFETCH_INST_PC_REL : SM_Prefetch_Pseudo <"s_prefetch_inst_pc_rel", SReg_64, 0>;
def S_PREFETCH_DATA : SM_Prefetch_Pseudo <"s_prefetch_data", SReg_64, 1>;
def S_PREFETCH_DATA_PC_REL : SM_Prefetch_Pseudo <"s_prefetch_data_pc_rel", SReg_64, 0>;
def S_BUFFER_PREFETCH_DATA : SM_Prefetch_Pseudo <"s_buffer_prefetch_data", SReg_128, 1> {
def S_BUFFER_PREFETCH_DATA : SM_Prefetch_Pseudo <"s_buffer_prefetch_data", SReg_128_XNULL, 1> {
let is_buffer = 1;
}
} // end let SubtargetPredicate = isGFX12Plus
Expand Down
6 changes: 6 additions & 0 deletions llvm/test/MC/AMDGPU/gfx1030_err.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -573,3 +573,9 @@ v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0]

v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1]
// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.

image_bvh_intersect_ray v[4:7], v[9:19], null
// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

image_bvh64_intersect_ray v[4:7], v[9:20], null
// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
2 changes: 2 additions & 0 deletions llvm/test/MC/AMDGPU/gfx10_asm_smem_err.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -84,3 +84,5 @@ s_buffer_load_dwordx16 s[4:19], null, s101
s_buffer_store_dword s4, null, s101
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

s_atc_probe_buffer 7, null, s2
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
6 changes: 6 additions & 0 deletions llvm/test/MC/AMDGPU/gfx11_asm_mimg_err.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -517,3 +517,9 @@ image_sample_o v[5:6], v[1:2], null, s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D

image_sample_o v[5:6], v[1:2], s[8:15], null dmask:0x3 dim:SQ_RSRC_IMG_1D
// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

image_bvh_intersect_ray v[4:7], v[9:19], null
// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

image_bvh64_intersect_ray v[4:7], v[9:20], null
// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
3 changes: 3 additions & 0 deletions llvm/test/MC/AMDGPU/gfx11_asm_smem_err.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,3 +29,6 @@ s_buffer_load_dwordx8 s[4:11], null, s101

s_buffer_load_dwordx16 s[4:19], null, s101
// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

s_atc_probe_buffer 7, null, s2
// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
5 changes: 5 additions & 0 deletions llvm/test/MC/AMDGPU/gfx12_asm_mimg_err.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -374,3 +374,8 @@ image_sample_o v[5:6], [v1, v2], null, s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
image_sample_o v[5:6], [v1, v2], s[8:15], null dmask:0x3 dim:SQ_RSRC_IMG_1D
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

image_bvh_intersect_ray v[4:7], [v9, v10, v[11:13], v[14:16], v[17:19]], null
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

image_bvh64_intersect_ray v[4:7], [v[9:10], v11, v[12:14], v[15:17], v[18:20]], null
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
18 changes: 18 additions & 0 deletions llvm/test/MC/AMDGPU/gfx12_asm_smem_err.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,3 +29,21 @@ s_buffer_load_dwordx8 s[4:11], null, s101

s_buffer_load_dwordx16 s[4:19], null, s101
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

s_atc_probe_buffer 7, null, s2
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

s_buffer_prefetch_data null, 100, s10, 7
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

s_buffer_load_i8 s5, null, s0
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

s_buffer_load_u8 s5, null, s0
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

s_buffer_load_i16 s5, null, s0
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

s_buffer_load_u16 s5, null, s0
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
Loading