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Interface Specification

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Peter Kazanzides edited this page May 9, 2024 · 64 revisions

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1. Overview

This page documents the interface between the Control PC and the FPGA1394 board inside the dVRK controller (with QLA or DQLA) or dVRK-Si controller (with dRAC). This interface was originally implemented via IEEE-1394 (Firewire) but is now also implemented via Ethernet (UDP).

The IEEE-1394 (Firewire) protocol supports two types of data transfer: Quadlet Transfer and Block Transfer. For quadlet transfers, a quadlet packet with address field is sent to the FGPA and the FGPA will either send the requested data back for the read case or have the write request executed. The quadlet transfer is often used for debugging or initialization of the FPGA connection. Because only one 32-bit register of the specified channel can be read or written, the quadlet transfer is not appropriate for reading and sending data in the robot servo control thread for performance reasons. In contrast, the block transfer supports reads and writes to a few key registers for all channels at one time.

Firewire defines a 48-bit address field, but the FPGA uses only the lowest 16 bits, with the most significant 4 bits (15-12) defining a sub-address space as follows (for Firmware Rev 4+):

ADDR Bits 15-12 Description (Quadlet I/O) Description (Block I/O)
ADDR_MAIN 0000 (0) Board and device (channel) registers Real-Time Block
ADDR_HUB 0001 (1) Broadcast Transfers
ADDR_PROM 0010 (2) FPGA PROM address space
ADDR_PROM_QLA 0011 (3) QLA (or dRAC) PROM address space
ADDR_ETH 0100 (4) Ethernet debug address space (Rev 6+)
ADDR_FW 0101 (5) Firewire debug address space (Rev 6+)
ADDR_DS 0110 (6) Dallas 1-wire memory (dV instrument) (Rev 7+)
ADDR_DATA_BUF 0111 (7) Data collection status (Rev 7+) Data collection buffer (Rev 7+)
ADDR_WAVEFORM 1000 (8) Waveform table for digital outputs (Rev 7+)

Older versions of Firmware are no longer supported. Prior to Rev 4, the FPGA PROM address space was indicated by setting bits 7:6 to 11.

Following are details for the sub-addresses:

Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0 Description
ADDR_MAIN (0) Reserved 0000 (0) REG Global (board) registers
ADDR_MAIN (0) Reserved CHAN (1-15) OFF Channel-specific registers
Bits 15-12 Bits 11-9 Bits 8-5 Bits 4-0 Description
ADDR_HUB (1) Reserved BoardNum ReadBlock Addresses array of Block Read data for each board
Bits 15-12 Bits 11-6 Bits 5-0 Description
ADDR_PROM (2) Reserved quad_addr (0-63) Address for block read or write
Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0 Description
ADDR_PROM_QLA (3) 0000 CHAN (0-15) 0000 Quadlet write to command register
ADDR_PROM_QLA (3) 0000 CHAN (0-15) 0001 Quadlet read of PROM status
ADDR_PROM_QLA (3) 0000 CHAN (0-15) 0010 Quadlet read of PROM result
ADDR_PROM_QLA (3) 0001 CHAN (0-15) quad_addr
(0-15)		 Address for block read or write
Bits 15-12 Bits 11-8 Bit 7 Bits 6-0 Description
ADDR_ETH (4) Reserved 0 quad_addr
(0-127)		 Addresses Firewire packet received via Ethernet
ADDR_ETH (4) Reserved 1 variable Addresses Ethernet debug data (see below)

The Ethernet debug data varies based on the FPGA board version and firmware version, and is only available when the firmware has been compiled with debug data enabled.

FPGA Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0 Description
V2, V3 ADDR_ETH (4) Reserved 1000 (8) addr EthernetIO debug data
V2 ADDR_ETH (4) Reserved 1001 (9) addr KSZ8851 debug data
V3 ADDR_ETH (4) 0 1001 (9) addr Ethernet switch
V3 ADDR_ETH (4) Port (1-4) 1001 (9) addr Low-level port debug
V2 ADDR_ETH (4) Reserved 1010 (a) addr KSZ8851 RunProgram
V3 ADDR_ETH (4) 0 1010 (a) addr Ethernet switch
V3 ADDR_ETH (4) Port (1-4) 1010 (a) addr Low-level port debug (continued)
V2 ADDR_ETH (4) Reserved 1010 (b) addr KSZ8851 RunProgram (continued)
V3 ADDR_ETH (4) 0 1011 (b) addr Ethernet switch
V2, V3 ADDR_ETH (4) Reserved 1100 (c) addr Received Ethernet packet
V2, V3 ADDR_ETH (4) Reserved 1101 (d) addr Reply Ethernet packet
V2, V3 ADDR_ETH (4) Reserved 1110 (e) addr EthernetIO ReplyIndex
V2, V3 ADDR_ETH (4) Reserved 1111 (f) addr EthernetIO ReplyIndex (continued)
Bits 15-12 Bits 11-7 Bits 6-0 Description
ADDR_FW (5) Reserved quad_addr
(0-127)		 Addresses Firewire packet received via Firewire
(only implemented in debug firmware)
Bits 15-12 Bits 11-6 Bits 5-0 Description
ADDR_DS (6) Reserved quad_addr (0-63) Address for block read
Bits 15-12 Bit 11 Bit 10 Bits 9-0 Description
ADDR_DATA_BUF (7) 0 X quad_addr (0-1023) Starting address for block read
ADDR_DATA_BUF (7) 1 0 0 Data collection status register (quadlet)
Bits 15-12 Bits 11-10 Bits 9-0 Description
ADDR_WAVEFORM (8) Reserved quad_addr (0-1023) Starting address for block write

2. Quadlet Transfers

All of the I/O resources are directly accessible by software via quadlet transfers, with the desired device specified by an appropriate value in the address field of the packet header. In all cases, the FPGA checks the destination ID field in the packet header and only acts if the value matches the local node ID, which is automatically assigned by the physical layer. Furthermore, it only acts if the specified transaction code is supported. Otherwise packets are considered inapplicable to the node and are silently ignored. When active, the FPGA reads data from or writes data to intermediate buffers.

The address field for quadlet transfers is interpreted as follows: bits 7-4 address a channel, while bits 0-4 address a device on that channel. The address map is listed in the table below. One detail of note is that channel devices begin at channel address 1, as channel address 0 specifies the global I/O module, whose address map is also shown in the table. Although the Quad Linear Amplifier (QLA) has only 4 channels, this interface specification has been defined to accommodate up to 15 channels. This enables the protocol to work with the dRAC, which has 10 channels (more specifically, it has 10 motor channels and 7 encoder channels). Detailed description of each register is available below.

Bits 7-4 Bits 3-0 Description (Read) Description (Write)
0 (Global Register) 0 Status Power and relay control
1 IEEE 1394 PHY Control Register IEEE 1394 PHY Control Register
2 IEEE 1394 PHY Data Register IEEE 1394 PHY Data Register
3 Watchdog Timeout Period Watchdog Timeout Period
4 FPGA Hardware Version
5 Amplifier Temperature
6 DOUT (digital output) status DOUT (digital output)
7 FPGA Firmware Version
8 PROM Status PROM Command
9 PROM Result N/A
10 Digital inputs (and output state)
11 IP Address IP Address
12 Ethernet Status Ethernet control
13 One-wire (Dallas) interface result One-wire (Dallas) interface control
14 Unused
15 Unused
1-4 (Channel Select) 0 ADC Data Register
1 DAC Control DAC Control
2 Unused
3 Unused
4 Quadrature Encoder Preload
5 Quadrature Encoder Data
6 Encoder Period Data Register
7 Encoder Quarter 1 Data Register
8 Digital OUT High/Low period
9 Encoder Quarter 5 Data Register
10 Encoder Running Counter (Rev 7+)
11 Motor Configuration Register (Rev 8+)
12 Motor Status Register (Rev 8+)
13-15 Unused

3. Block Transfers

This section documents the Real-Time Block Transfers that are used for motor control. The Control PC obtains feedback data by performing Block Read, computes the control signals (motor currents) and then performs a Block Write. The Real-Time Block Transfers are performed by writing to ADDR_MAIN (0). Note that only bits 15-12 must be set to 0 (the FPGA firmware ignores bits 11-0), but by convention an address of 0 should be used.

The following tables depict the block read and write packet formats expected by the FPGA, as well as how it interprets the data fields. The FPGA firmware was originally designed to handle write blocks of a fixed size due to the simplicity and reliability of such an approach. Thus, the MSB of each Motor Current data quadlet is interpreted as a valid bit, which is set by software to indicate to the FPGA whether or not the corresponding device is to be written. Starting with Firmware Rev 8, and the introduction of the dRAC (dVRK-Si), the write block is no longer fixed size and therefore it contains a header quadlet that specifies the block length (in quadlets).

Please note that N (number of axes/channels) is chosen to be 4 for the QLA, but can be changed to support other hardware. The block read data should have 4N+4 quadlets (for Firmware Version 1-6) or 6N+4 quadlets (for Firmware Version 7) and the block write data should have N quadlets (for Firmware Version 1-6, where the PC software allocates N+1, but only sends a block of size N, as explained below) or N+1 quadlets (for Firmware Version 7). Starting with Firmware Version 8, N is replaced by Nm (number of motors) and Ne (number of encoders). For the QLA, Nm = Ne = 4 and for the DQLA (dual QLA), Nm = Ne = 8, whereas for the dRAC, Nm = 10, Ne = 7. The block read size is 2Nm+5Ne+4 quadlets and the block write size is Nm+1 quadlets.

Block reads/writes are also performed for other purposes, such as reading/writing the FPGA PROM, QLA PROM, and Dallas 1-wire memory, which are described elsewhere.

3.1 Block Read Packet Format

Quadlet QLA DQLA dRAC Field (Rev 1-5) Field (Rev 6) Field (Rev 7 ) Field (Rev 8-9)
0 0 0 0 Timestamp Timestamp Timestamp Timestamp
1 1 1 1 Status Status Status Status
2 2 2 2 Digital I/O Digital I/O Digital I/O Digital I/O
3 3 3 3 Temperature Temperature Temperature Temperature
4 4 4 4 Pot / Cur 1 Pot / Cur 1 Pot / Cur 1 Pot / Cur 1
... ... ... ... ... ... ...
4+Nm-1 7 11 13 Pot / Cur N Pot / Cur N Pot / Cur N Pot / Cur Nm
4+Nm 8 12 14 Encoder 1 Encoder 1 Encoder 1 Encoder 1
... ... ... ... ... ... ...
4+Nm+Ne-1 11 19 20 Encoder N Encoder N Encoder N Encoder Ne
4+Nm+Ne 12 20 21 Encoder Vel (DT) 1 Encoder Vel (DT)+Q1 1 Encoder Vel (DT) 1 Encoder Vel (DT) 1
... ... ... ... ... ...
4+Nm+2Ne-1 15 27 27 Encoder Vel (DT) N Encoder Vel (DT)+Q1 N Encoder Vel (DT) N Encoder Vel (DT) Ne
4+Nm+2Ne 16 28 28 Encoder Vel (DP) 1 Encoder Accel Q1+Q5 1 Encoder Accel Q1 1 Encoder Accel Q1 1
... ... .... ... ... ...
4+Nm+3Ne-1 19 35 34 Encoder Vel (DP) N Encoder Accel Q1+Q5 N Encoder Accel Q1 N Encoder Accel Q1 Ne
4+Nm+3Ne 20 36 35 Encoder Accel Q5 1 Encoder Accel Q5 1
... ...
4+Nm+4Ne-1 23 43 41 Encoder Accel Q5 N Encoder Accel Q5 Ne
4+Nm+4Ne 24 44 42 Encoder Running Counter 1 Encoder Running Counter 1
... ...
4+Nm+5Ne-1 27 51 48 Encoder Running Counter N Encoder Running Counter Ne
4+Nm+5Ne 28 52 49 Motor Status 1
...
4+2Nm+5Ne-1 31 59 58 Motor Status Nm

3.2 Block Write Packet Format

A block write to one board consists of the following packet. For a broadcast block write, multiple packets (one for each board) are concatenated into a single packet.

Quadlet QLA dRAC Field (Rev 1-7) Field (Rev 8-9)
0 0 0 Valid, Board-id, Motor Current 1 Header (board-id, num-quadlets)
1 1 1 Valid, Board-id, Motor Current 2 Valid, Motor Current 1
... ... ... ...
Nm-1 3 9 Valid, Board-id, Motor Current N Valid, Motor Current Nm-1
Nm 4 10 Power / Relay Control (*) Valid, Motor Current Nm
Nm+1 5 11 Power / Relay Control

Valid: Most significant bit (Bit 31) must be set to 1; otherwise, firmware will ignore the motor current

Board-id: Bits 27-24 must be set to board-id (prior to Firmware Rev 8); otherwise, firmware will ignore the motor current (this safety check was introduced for the broadcast write)

* Firmware Rev 1-6 does not support the Power/Relay Control field, thus the mechatronics software sends this field separately as a quadlet write command. The Rev 7+ firmware includes this field, but only sends the lower 20 bits, which are the ones used for power and relay control (the upper 12 bits are set to 0). For dRAC, only bits 19-16 are used; the lowest 16 bits (15-0) are unused.

Firmware Rev 8+ adds a header quadlet at the beginning of each packet. The format is:

Bits 31-12 Bits 11-8 Bits 7-0
Unused (0) board id number of quadlets (Nm+2)

3.3 Timestamp

A 32-bit counter records the time interval between each block read in counts (clock = 49.152 MHz).

 Example: Sample block read
 ~@: ./block1394 0 20
   0x01492252  (timestamp)
   0x46830000
   ......
   ......

In this sample block read, the timestamp field is 0x01492252, which is 0.439 seconds.

4. Global Register Descriptions

Register 0: Status (Read)

This 32-bit status register provides board status information. Many of the fields are hardware-specific and therefore vary between the currently supported companion boards (QLA, DQLA and dRAC). It is important for bits 27-24 to contain the board id (rotary switch) because this is assumed when scanning the bus. The software also assumes that the watchdog timeout is indicated in bit 23.

The meaning for each bit is shown in the following table. Note that many fields are only relevant for the QLA (unused for dRAC).

Bit Description QLA DQLA dRAC
31-28 Number of channels 4 8 10
27-24 Rotary Switch
23 Watchdog Timeout
22 Board-specific DAC type (Rev 8+) DAC type, QLA 2 Is ECM
21 Board-specific DOUT cfg valid (Rev 5+) DAC type, QLA 1 Unused (0)
20 Board-specific DOUT cfg (Rev 5+) Unused (0) Unused (0)
19 Board-specific Motor voltage good Motor voltage good (QLA 1+2) Motor voltage good
18 Board-specific Power enable control Power enable control (QLA 1+2) Power enable control
17 Board-specific Safety relay status Unused (0) Safety relay status
16 Board-specific Safety relay control Safety relay control (QLA 1+2) Safety relay control
15 Board-specific Motor pwr fault (Rev 6+) Motor voltage good (QLA 2) Unused (0)
14 Board-specific Safety circuit (Rev 8+) Motor voltage good (QLA 1) Safety circuit (Rev 8+)
13 Board-specific Unused (0) DQLA IO-exp ok (QLA 2) Unused (0)
12 Board-specific QLA IO-exp present (Rev 8+) DQLA IO-exp ok (QLA 1) Unused (0)
11 Board-specific QLA amp status 4 DOUT config valid (QLA 2) Unused (0)
10 Board-specific QLA amp status 3 DOUT config valid (QLA 1) Unused (0)
9 Board-specific QLA amp status 2 DOUT config (QLA 2) Unused (0)
8 Board-specific QLA amp status 1 DOUT config (QLA 1) Unused (0)
7 Board-specific QLA amp safety 4 Safety circuit (QLA 2) Unused (0)
6 Board-specific QLA amp safety 3 Safety circuit (QLA 1) Unused (0)
5 Board-specific QLA amp safety 2 Motor supply fb (QLA 2) Unused (0)
4 Board-specific QLA amp safety 1 Motor supply fb (QLA 1) Unused (0)
3 Board-specific QLA amp enable 4 Reserved Encoder preload good
2 Board-specific QLA amp enable 3 Unused (0) ESPM 6V good
1 Board-specific QLA amp enable 2 QLA IO-exp present (QLA 2) ESII/ESCC comm WDT good
0 Board-specific QLA amp enable 1 QLA IO-exp present (QLA 1) ESPM comm WDT good
Field name Description
DAC type 0=4xLTC2601, 1=1xLTC2604
DOUT cfg Digital output configuration: 0=MOSFET, 1=Bidirectional
Motor pwr fault 1=motor power fault detected (Rev 6+, with QLA 1.4+)
Safety circuit 1=safety circuit voltage present (Rev 8+, with QLA 1.5+)
QLA IO-exp present 1=detected MAX7317 I/O expander on QLA (present on QLA Rev 1.5+)
DQLA IO-exp ok 1=successfully initialized MAX7301 I/O expander on DQLA (one for each QLA)
QLA amp status 0=fault, 1=enabled (deprecated in Rev 8+, use Motor Status register instead)
QLA amp safety 1=amplifiers disabled due to feedback current check (deprecated in Rev 8+, use Motor Status register instead)
QLA amp enable 1=amplifier enable request (deprecated in Rev 8+, use Motor Status register instead)
Motor supply fb Used to determine motor supply voltage (QLA 1.5+)

The QLA digital output configuration (DOUT config) is auto-detected by the firmware (Rev 5+), and distinguishes between the bidirectional transceiver design (QLA Rev 1.4+) and the MOSFET open drain design (prior QLA versions). Note that an FPGA with firmware version less than 5 cannot control the digital outputs for QLA Rev 1.4+ because they are configured as inputs on power-up and the firmware must explicitly configure them as outputs.

QLA Rev 1.5+ supports two DAC configurations: 4 x LTC2601 (4 single channel DACs, as in prior QLA versions) or 1 x LTC2604 (1 quad DAC). The firmware detects which configuration is used based on whether the DAC MOSI pin is pulled low (for LTC2604) and reports the configuration (DAC type) in the status register.

QLA Rev 1.5+ contains an I/O Expander (MAX7317) that is auto-detected by the firmware (Rev 8+).

Rotary Switch

A rotary switch is available on each FPGA controller board. Its value can be used as the identifier for each board set, when multiple board sets are daisy-chained to control more than 4 motors. This is important because the computer program needs to specify the destination ID in the packet header, which is automatically assigned by the IEEE-1394 physical layer. The rotary switch value is bits 24-27 in the Status data. In the example Status read, the rotary switch is set to 5.

 ~@: ./quad1394 0
    0x45000000

Register 0: Status (Write)

The status register can be written to enable/disable power and relays. Many of the fields are hardware-specific and therefore vary between the currently supported companion boards (QLA, DQLA and dRAC). Bits 21-20 (software reset/reboot) are used for all configurations because they involve only the FPGA.

The bits definitions are as follows:

Bit Description
31-25 Unused (0)
24 1 -> redetect QLA digital output configuration (Rev 7+)
23 1 -> redetect QLA I/O expander (Rev 8+, was unused mask for eth1394 mode, Rev 5-6 firmware)
22 1 -> redetect QLA DAC type (Rev 8+, was unused eth1394 bit in Rev 5-6 firmware)
21 Mask for software reset/reboot
20 Global reset (Rev 1-6), reboot (Rev 7+)
19 Mask for power enable
18 Power enable control
17 Mask for safety relay
16 Safety relay control
15-12 Unused (0)
11-8 Masks for QLA amplifier enable
7-4 Unused (0)
3-0 QLA Amplifier enable control

Enable / Disable Motor Power

The QLA and dRAC boards have two level power control. The FPGA can control the amplifier board’s motor voltage regulator chip to turn on/off the motor voltage power for the entire board. For the QLA, a control pin is connected to each Op-Amp’s E/S pin, thus providing amplifier enable/disable control for each individual axis. Similarly,the dRAC has a signal to enable/disable each amplifier. The board level power is set by the power enable control bit, and the axis level power enable can be controlled by changing the amplifier enable bits. The indicator LED will be turned on if the corresponding axis is enabled.

 Example 1: Enable board level power (bit_19 = 1 bit_18 = 1)

 ~@: ./quad1394 0 0xC0000

 Example 2: Disable board level power (bit_19 = 1 bit_18 = 0)

 ~@: ./quad1394 0 0x80000

 Example 3: Enable motor power for Axis 3

 ~@: ./quad1394 0 0404

 Example 4: Disable motor power for Axis 3

 ~@: ./quad1394 0 0400

Enable / Disable RELAY

One relay is built in each QLA or dRAC board as a safety feature, which can be controlled by RELAY_ON signal from FPGA chip. The following examples show how to enable, disable and check the relay. Let's assume there is only one FPGA_QLA board set connected and has default node id (0).

 Example 1: Enable RELAY (Mask bit_17 = 1, Control bit_16 = 1)

 ~@: ./quad1394 0 0x30000

 Example 2: Disable RELAY (Mask bit_17 = 1, Control bit_16 = 0)

 ~@: ./quad1394 0 0x20000

 Example 3: Read RELAY status (Status bit_17 = 1, Control bit_16 = 1)

 ~@: ./quad1394 0
   0x45030000

Global Reset / Reboot FPGA

For Rev 1-6, the global reset bit causes many of the FPGA registers to be reset to their initial values. For Rev 7+, this bit causes the FPGA to reboot, which is useful after a new firmware version has been programmed. Reboot is currently not supported for FPGA Rev 3+.

Registers 1-2: Physical Layer Chip Read and Write

Access to the IEEE-1394 (Firewire) Physical Layer (PHY) chip is an advanced feature (use with caution). Send a command through the Control Register (1) and read from the Data Register (2). In mechatronics-firmware (Verilog), these are defined as REG_PHYCTRL and REG_PHYDATA, respectively, whereas in mechatronics-software (C++), these are defined as FW_PHY_REQ and FW_PHY_RESP, respectively. All FireWire PHY registers are 8-bits wide.

Write to FireWire PHY register

To write Data to the register specified by Addr, use the following format when writing to FW_PHY_REQ (1):

Bits 31-13 Bit 12 Bits 11-8 Bits 7-0
Reserved (0) 1 Addr Data

Read from FireWire PHY register

To read from the register specified by Addr, first use the following format when writing to FW_PHY_REQ (1):

Bits 31-13 Bit 12 Bits 11-4 Bits 3-0
Reserved (0) 0 Reserved (0) Addr

Then, read the result (Data) from FW_PHY_RESP (2):

Bits 31-16 Bits 15-12 Bits 11-8 Bits 7-0
Reserved (0) Status Addr Data

Note that Addr should be equal to the value written to FW_PHY_REQ and Status provides low-level FireWire status information (not expected to be of interest):

Bit Description
15 ARB_RESET_GAP
14 SUBACTION_GAP
13 BUS_RESET_START
12 PHY_INTERRUPT 
 Example 1: Read PHY register 0 by writing to register 1 and then reading from register 2
 ~@: ./quad1394 1 0
 ~@: ./quad1394 2
    0x00000004  

 # The format of Register 0 is | 6: physical ID | 1:R | 1:PS |
 # 0x00000004 -> Data = 0b00000100, so physical id = 0b000001, R = 0 PS = 0

Reference: Book Chapter 11/22

Register 3: Watchdog

A 16-bit watchdog is available on each FPGA board. The watchdog counter will be reset when a write packet is received. When a watchdog timeout occurs, all four amplifiers are disabled and the Watchdog Timeout bit (23) is set in the status register. One bit in the watchdog counter corresponds to about 5.2 us, for a maximum watchdog period of about 340 ms. If the watchdog period is set to 0x0000, then the watchdog will be disabled. The watchdog period can be read and written via quadlet read/write commands. Starting with Firmware Rev 6, the watchdog timeout bit is cleared by any write command that requests board power to be enabled and/or any amplifier to be enabled, regardless of whether the command is successful. In prior versions of firmware, this bit was cleared by any write to the board.

 Example 1: Write watchdog period to 0x1FFF (About 42 ms)
 ~@: ./quad1394 03 0x1FFF

 Example 2: Read watchdog period 
 ~@: ./quad1394 03
    0x00001FFF

Register 4: Hardware Version

 ~@: ./quad1394 4
    0x514C4131

Quadlet read from 0x04 will return the hardware version. For the QLA, the return value is 0x514C4131 = "QLA1" (ASCII). For the dRAC, the return value is 0x64524131 = "dRA1" (ASCII). For the DQLA, the return value is 0x44514C41 = "DQLA" (ASCII).

Register 5: Temperature

The quadlet transfer with address 0x05 will read the MAX6576 temperature sensors that are located on the QLA motor power amplifier heat sink. Bits 0-7 and 8-15 give the readings from sensors one and two, respectively, on the QLA (or QLA 1 in the DQLA setup). For the DQLA, bits 16-23 and 24-31 give the readings from sensors one and two, respectively, on QLA 2. Dividing each reading by 2 gives the temperature in degrees Celsius. Note that for the QLA, the upper 16-bits are used for Data Collection Status (described below).

Example: Quadlet temperature read, T1 = 0x3F/2 = 31.5 deg T2 = 0x3D/2 = 30.5 deg

 ~@: ./quad1394 5
    0x003D3F

Register 5 (MSW): Data Collection Status (Rev 7+, QLA only)

Starting with Firmware Rev 7, the most significant word (upper 16 bits) of Register 5 contains the data collection status. For previous versions of Firmware, this field is 0. The format is the following (where bit 15 is the most-significant bit of the word, which is the same as bit 31 of the quadlet):

Bits Description
15 1 -> Data collection is active
14 Reserved (0)
13-10 Channel being collected (1-4)
9-0 Next entry to be written (0-1023)

Register 6: Digital Output

A quadlet write to address 0x06 will change the state of the digital outputs that are specified by the associated mask bit. The 32-bit value is interpreted as follows:

Bits 31-16 Bits 15-8 Bits 7-0
Unused Mask Value

It is necessary to set the Mask bit to 1 to be able to set the corresponding digital output to the specified Value. For the QLA, Mask bits 15-12 and Value bits 7-4 are not used. For the DQLA, they are used to set the digital outputs for QLA 2.

Reading from address 0x06 returns the current values of the digital outputs (there are no mask bits).

Example 1: Set DOUT1 to 1

~@: ./quad1394 6 0011

Example 2: Set DOUT2 to 0

~@: ./quad1394 6 0020

Register 7: Firmware Version

 ~@: ./quad1394 7
    0x00000001

Quadlet read from 0x07 will return the firmware version.

Register 8: PROM Status/Command

The FPGA board (Rev 1.x or 2.x) contains a M25P16 PROM that stores the Firmware. Memory after the firmware image can be used to store additional information. Currently, PROM address 001FFF00 is used to store the string "FPGA" followed by a space and the board serial number. FPGA Rev 3.x does not contain this PROM.

When writing to this register, the 8 MSB are the Command (see table below) and the 24 LSB are the PROM address.

Command Description
00 Idle (NOP)
01 Write Status Register
02 Write
03 Read
04 Write Disable
05 Read Status Register
06 Write Enable
0B Fast Read Data (256 bytes)
9F Read Identification
AB Wake (Release from Deep Power Down)
B9 Deep Power Down
C7 Block Erase
D8 Sector Erase
FF Debug (see M25P16.v)

Reading from this register provides the Status of the interface, which primarily consists of debug data (see M25P16.v). Bits 2-0 are the state (000=IDLE) and Bit 3 indicates whether a block write is in progress. Thus, completion of a block write command can be determined by checking that the 4 LSB are 0.

Register 9: PROM Result

Reading from register 0x09 returns the result of the last command sent to the M25P16 PROM:

  • For a PROM read, it returns the number of quadlets available (0-127). Currently, this should always be 64 because the Firmware reads 256 bytes at a time from the PROM and stores it in FPGA memory (as 64 quadlets). Once the software confirms that bytes are available, a block read is performed to the PROM_ADDR sub-address.
  • For a PROM write, it returns the number of quadlets written (0-127). Note that the first quadlet contains the Write command (02) and address, so to program 64 quadlets (256 bytes), it is necessary to send 65 quadlets.
  • For a Read Status Register command (05), it returns the contents of the 16-bit status register. Bit 0 is the Write In Progress (WIP) bit.
  • For a Read Identification command (9F), it returns the first 3 bytes of the Chip ID.

Register 10: Digital Input/Output Value

Read current digital input/output from address 0x0A. Note tha this data is also available in block transfer. The digital inputs are hardware-specific and vary between the QLA, DQLA and dRAC. Note that the high bit number always maps to high axis number. For example, data[3] is home for axis 4 on the QLA.

# read digital input/output value
 ~@: ./quad1394 0x0A

The following tables define the bits for the QLA and DQLA. Note that the lowest 16-bits are the same for QLA and DQLA.

Bit Description (QLA)
31 V-Fault (short in encoder circuit)
30 Unused (0)
29 Waveform table active (Firmware Rev 7+)
28 Motor supply voltage feedback (Firmware Rev 8+)
27-24 Encoder Channel A
23-20 Encoder Channel B
19-16 Encoder Index
15-12 Digital Output
11-8 Negative Limit
7-4 Positive Limit
3-0 Home Limit
Bit Description (DQLA)
31-28 Digital Output (QLA 2)
27-24 Negative Limit (QLA 2)
23-20 Positive Limit (QLA 2)
19-16 Home Limit (QLA 2)
15-12 Digital Output (QLA 1)
11-8 Negative Limit (QLA 1)
7-4 Positive Limit (QLA 1)
3-0 Home Limit (QLA 1)

Register 11: IP Address

For Firmware Rev 7+, the Ethernet IP address (as a 32-bit number) can be set by writing to address 0x0B (11) and the current IP address can be obtained by reading address 0x0B (11). On power-up, the FPGA initializes the IP address to 0xffffffff.

Register 12: Ethernet Status/Control

This register provides Ethernet status feedback and is also used to distinguish between the major revisions of the FPGA1394 board, which have different numbers of Ethernet ports (0 for V1, 1 for V2 and 2 for V3).

The register was initially created to provide access to the low-level Ethernet hardware, specifically the KSZ8851 10/100 Mbps Ethernet controller chip on FPGA V2. It has been extended to provide status feedback for FPGA V3.x, which has two RTL8211F Ethernet PHY chips. However, for FPGA V3.x, the debug interface to the RTL8211F PHYs is instead provided by a register in the ADDR_ETH space.

Ethernet Status (Read)

Bit assignments when reading from the register (all bits are 0 for FPGA V1):

Bits FPGA V2 FPGA V3 Description
31 1 0
30 ReqErr 1 V2: Unable to access KSZ8851 registers
29 InitOK 0 V2: PHY initialization successful; V3: Reserved (was EthPort in Rev 8)
28 FrameErr FrameErr Unsupported Ethernet frame (not Raw, IPv4 or ARP)
27 IPv4Err IPv4Err IPv4 header error (protocol not UDP or ICMP or header version not 4)
26 UDPErr UDPErr UDP port not 1394
25 DestErr DestErr Incorrect destination address
24 AccessErr AccessErr Unable to access internal bus on FPGA
23 StateErr Clk125OK V2: Invalid state in link layer (KSZ8851) state machine; V3: 125 MHz clock ok, Rev 9
22 EthStateErr EthStateErr Invalid state in Ethernet send/receive state machine
21 Unused (0) Clk200OK V3: 200 MHz clock ok
20 UDP UDP System is operating in UDP mode (1) or Raw mode (0)
19 LinkStat Unused (0) V2: 1 -> Link On (for V3, see PortStatus below)
18 EthIdle Unused (0) V2: 1 -> link layer (KSZ8851) state machine is idle
17 WaitInfo 0 V2: State machine is waiting to receive (1), send (2) or flush (3)
16 * PsEth V3: PS Ethernet enabled, Rev 9
15-8 RegData Port Status[2] V2: Result of register read; V3: Status for Eth2
7-0 RegData Port Status[1] V2: Result of register read; V3: Status for Eth1

The Port Status bits (for Eth1 and Eth2) are defined as follows:

Bits FPGA V3 Description
7 InitOK PHY initialization successful
6 hasIRQ 1 -> PHY IRQ is connected to FPGA (V3.1+)
5 LinkStat 1 -> Link On
4:3 LinkSpeed Link operating at 10 Mbps (0), 100 Mbps (1), 1000 Mbps (2)
2 0 Reserved (was RecvErr in Rev 8)
1 0 Reserved (was SendOvf in Rev 8)
0 0 Reserved (was PsEth in Rev 8)

Ethernet Control (Write)

Bit assignments when writing to the register for FPGA V2 and V3:

Bits FPGA V2 Description
31-30 0 Reserved
29 ClearErrN Clear network layer (EthernetIO) errors
28 ClearErrL Clear link layer errors
27 DMA DMA request
26 Reset Reset KSZ8851 PHY
25 R/W Read(0) or Write(1)
24 W/B Word(1) or Byte(0)
23-16 Addr 8-bit address
15-0 Data 16-bit data
Bits FPGA V3 Description
31 0 Reserved
30 ClearErrS Clear Ethernet switch errors, Rev 9
29 ClearErrN Clear network layer (EthernetIO) errors
28 MaskL Mask for Port Control bits
27 MaskIRQ Mask for Port IRQ disable
26 MaskReset Mask for Port reset
25 MaskPsEth Mask for Port PS Ethernet enable
24-17 0 Reserved
16 1 Enable(1)/Disable(0) PS Ethernet (if MaskPsEth also set), Rev 9
15-8 Port Control[2] Eth2 Port Control
7-0 Port Control[1] Eth1 Port Control

The Port Control bits (for Eth1 and Eth2) are defined as follows:

Bits FPGA V3 Description
7 Reset Reset RTL8211F PHY (if MaskReset also set)
6 IRQdisable Disable IRQ from PHY (if MaskIRQ also set)
5 IRQsw Generate software IRQ (if MaskL also set)
4 0 Reserved (was ClearErrors in Rev 8)
3 0 Reserved
2 0 Reserved (was RecvFifoReset in Rev 8)
1 0 Reserved (was SendFifoReset in Rev 8)
0 0 Reserved (was PsEth in Rev 8)

Note that for FPGA V2, the Ethernet Control register can only be written to via the Firewire interface to avoid contention for the KSZ8851 PHY. The only exception is bit 29 (ClearErrN), which can also be written via the Ethernet interface. For FPGA V3, all bits can be written via both the Firewire and Ethernet interfaces (since there are two Ethernet interfaces), but care should be taken to avoid contention for the same RTL8211F PHY.

Example for FPGA V2

For Firmware Rev 5+, the FireWire interface can be used to access the KSZ8851 chip on FPGA V2.x via this register, including chip register read and write (note that it is not reasonable to use the Ethernet interface to attempt to access the KSZ8851).

Write to this register to issue a read/write to the KSZ8851 register, then read back the result from this register (i.e., the Ethernet Status register).

Example: Read KSZ8851 Chip ID (CID)

# 1 Quadlet write to select KSZ8851 Chip ID and Enable Register (0xC0)
./quad1394 0x0C 0x01C00000

# 2 Read the result   
./quad1394 0x0C

# Returns 0xA01C8872
# Lowest 16-bits (0x8872) are the returned register value
# (Upper 16 bits are status/debug information)

Register 13: Dallas Chip

Starting with Firmware Rev 7, this register contains information related to the one-wire interface to the Dallas DS2505 chip (e.g., inside da Vinci instruments). This register is only used for the QLA, since the dRAC obtains the instrument information via an LVDS interface. For the QLA, there are two options to interface to the DS2505 chip: (1) a direct 1-wire interface, and (2) via serial communication to a DS2480B driver chip, either on the dMIB or on an attached "dongle". The direct 1-wire interface is hard-coded to use DOUT3, and since it requires bidirectional control, it is necessary to have QLA Version 1.4+. The firmware automatically detects the dout configuration; if bidirectional I/O is available, the dout_cfg bit below (bit 3) is set to 1. For the DS2480B interface, the FPGA uses DOUT3 to send data to the DS2480B and POSLIM3 to receive data from the DS2480B. Firmware Rev 8+ auto-detects whether the DS2480B is present and sets the useDS2480B bit as described below. With Firmware Rev 7, it is only possible to use the direct 1-wire interface.

Following is the format for reading the register:

Firmware Rev 7:

31-24 23-16 15-12 11-8 7-4 3 2-1 0
family code rise time unused (0) next state current state dout_cfg reset enabled

Firmware Rev 8+:

31-24 23-16 15 14 13 12-9 8-4 3 2-1 0
family code rise time useDS2480B unused (0) idle unused (0) current state dout_cfg reset enabled

Descriptions of the register fields are as follows:

Field Description
family code Family code read from the chip (0x0B for DS2505)
rise time Measured rise time, after chip reset, 20.345 nsec/bit (if !useDS2480B)
useDS2480B 1 if using autodetected DS2480B driver chip
busy 1 if firmware state machine is idle (Firmware Rev 8+)
next state Next state for state machine (debugging)
current state Current state for state machine (debugging)
dout_cfg 1 if bidirectional I/O available (QLA 1.4+)
reset Reset status: see table below
enabled 1 if 1-wire interface is currently enabled
Reset status Description
0 Reset not yet attempted
1 Successful reset
2 Failed: 1-wire did not rise within 5 usec after reset
3 Failed: no ack (low pulse within 300 usec) from DS2505

Note that the current state field is 4-bits in Rev 7 and 5-bits in Rev 8+. For Rev 7, the host PC had to check this field to determine if the state machine was idle (current state = 0) or busy (current state non-zero). For Rev 8+, the host PC can instead check the busy bit.

Bits 23-16 contain the measured rise time when using the direct 1-wire interface. When using the DS2480B driver, this field contains the most recently received input byte (for debugging).

Following is the format for writing the register:

31-27 26-16 15-4 3 2 1-0
unused (0) address (0-2047) unused (0) block_end unused (0) command

The block_end bit is only present in Firmware Rev 8+ and must be used to indicate the end of a block write for the DS2480B interface.

The command values are:

Bits 1-0 Description
00 Disable interface (release control of DOUT3)
01 Enable interface (take control of DOUT3)
10 Enable, initialize and read first 64 bytes from memory address
11 Continue reading next 64 bytes

Register 15: Git Describe

This register provides information about the status of the git source tree when the firmware was built, relative to tags named "RevG", where G is the version number. This register was introduced after Firmware Rev 8, so all versions up to and including Rev 8 return 0. The format of the register is:

31-4 3 2 1-0
SHA D C R

The SHA bits are the git SHA of the last commit (7 hexadecimal digits)

The D ("dirty") bit is 1 if there were uncommitted changes in the git source tree.

The C (commits) bit is 1 if there were any commits since the last Rev tag.

The R bits indicate the relationship between the firmware version reported by Register 7 (F) and the version (G) of the most recent git tag, "RevG":

1-0 Relationship Meaning
0 F == G Actual release,"F", or post-release update, "F+" (if D or C)
1 F == G+1 Pre-release firmware "F-"
2 F > G+1 Should not happen, "F?"
3 F < G Should not happen, "F?"

5. Channel Register (Offset) Descriptions

Offset 0: ADC Feedback

The ADC Feedback consists of a 16-bit motor current and a 16-bit analog input (e.g., potentiometer), as described below. The motor current is the least significant 16-bits and the analog input is the most significant 16-bits.

Motor Current Feedback

Motor current can be read from a 16-bit analog-to-digital converter (ADC) LTC1864. ADC counts reading 0x0000, 0x8000 and 0xFFFF correspond to motor currents -6.25 A, 0.00 A and +6.25 A, respectively, and the following equation converts ADC counts (Icnt) to mA (Im).

 Im = 6250 * 2 / (0xFFFF - 0x0000)Icnt - 6250 = 0.190737Icnt - 6250

Example: Sample motor current quadlet read for Axis 3

 ~@: ./quad1394 30
    Pot: 0x047F
    Cur: 0x7FBD

The motor current for Axis 3 is Im = 0x7FBD × 0.190737 − 6250 = −12.71 mA.

Analog (e.g., Potentiometer) Feedback

The analog input feedback uses a reference voltage of 4.5 V and its reading can be obtained from ADC LTC1864. The following equation converts ADC counts (Vcnt) to Volts (Vm):

 Vm = (4.5 - 0.0) / (0xFFFF - 0x0000)Vcnt = 0.00006866559Vcnt

Example: Sample potentiometer voltage quadlet read for Axis 3

 ~@: ./quad1394 30
    Pot: 0x047F
    Cur: 0x7FBD

The analog input for Axis 3 is Vm = 0x047F × 0.00006866559 = 0.079 V. If the analog input is a potentiometer voltage, you will also need hardware specific information to convert the POT voltage into either translation or rotation units.

Offset 1: DAC Motor Currents

For each QLA axis, a 16-bit LTC2601 digital-to-analog (DAC) is used to output the commanded motor current. The relationship between DAC counts and commanded motor current is shown in the following table. For QLA 1.5+, it is possible to use the DAC to specify motor voltage, instead of current. Also, QLA 1.5+ can use either 4xLTC2601 (1 per channel), or 1xLTC2064 quad DAC for all 4 channels. The dRAC uses PWM duty cycle, rather than a DAC, to specify either the commanded motor voltage or current.

DAC Counts QLA Motor Current QLA 1.5+ Motor Voltage
(cur_ctrl = 1) (cur_ctrl = 0)
0x0000 -6.25 A -45.5 V
0x8000 0.00 A 0.0 V
0xFFFF +6.25 +45.5 V

Note that the above specified currents or voltages may be limited due to hardware, including the motor power supply voltage and the motor resistance.

Firmware Rev 8+ register format:

Bit Description
31 valid (setpoint mask)
30 collect data
29 axis enable mask
28 axis enable
27-24 control mode, 0=current; 1=voltage/duty cycle
23-0 setpoint, right-aligned

Example: Set Axis 3 motor current to +254 mA

 ~@: ./quad1394 31 8500

Offset 4: Encoder Preload

Preload encoder counts into the encoder register in the FPGA.

Example: Preload 0x7FFFF to encoder register for Axis 3

 ~@: ./quad1394 34 0x7FFFFF
    0x007FFFFF

This command changes the axis 3 encoder preload to 0x7FFFFF.

Offset 5: Encoder Counts

The FPGA1394 QLA controller board supports quadrature encoder input and gives incremental position measurements in counts. The 24-bit encoder counter will overflow when the count drops below 0 or increases beyond 0xFFFFFF, so it is important to either preload the counter with the midpoint value (0x7FFFFF) during initialization or manage the underflow/overflow in software. The unit conversion equation is

 ENCsi = EncoderCountsPerTurn x GearRatio x Pitch x (ENCcnt - ENCpreload),

where ''EncoderCountsPerTurn'' is encoder counts per motor revolution, ''GearRatio'' is gear box ratio and ''Pitch'' is translational movement per turn for prismatic joint and 1 for revolute joint.

Example: Read encoder counts for Axis 3 using quadlet read

 ~@: ./quad1394 35
    0x007FFFFF

Offset 6: Encoder Velocity (DT)

This register reports the time between transitions of consecutive encoder pulses of the same type (1/∆Time method, also called DT), which is inversely proportional to the encoder velocity. Because the time is measured between encoder pulses of the same type, this corresponds to 4 counts, so the velocity in counts/second is given by 4/DT. This register is present in all version of firmware, but there are some differences in the details (number of bits, whether signed or with a separate sign bit, how overflow is indicated, clock sampling frequency and resulting time resolution, and edges measured), as specified in the following table. In addition, Firmware Versions 1-3 only measure the time between consecutive rising edges on encoder channel B (B-up to B-up), whereas Versions 4+ measure the time between all consecutive edges (i.e., A-up to A-up, A-down to A-down, B-up to B-up, B-down to B-down), so measurements are updated more frequently (however, implementations prior to Version 6 are not well tested).

Parameter Version 1-5 Version 6 Version 7+
Bits 16 22 26
Sign Signed Bit 30 Bit 30
Overflow 0x8000 Bit 31 Bit 31
Clock Freq. 768 kHz 3.072 MHz 49.152 MHz
Resolution ~1.3 usec ~0.3255 usec ~20.3 nsec

Also, in Firmware Version 6, bits 29-22 contain the lower 8 bits of the most recent quarter cycle period (Q1), which was moved to the Encoder Accel Q1 register starting in Firmware Version 7.

See the Encoder Velocity section for more information.

Example: Read velocity (DT) for Axis 3 using quadlet read

 ~@: ./quad1394 36
    0xFFFFFFF

Offset 7: Encoder Velocity (DP) or Encoder Accel Q1

For Firmware Versions 1-5, this register reports the number of encoder pulses in a given time interval (∆Position/∆Sample method, also called DP). But, this measurement was never used by the higher-level software so has been replaced by a different value.

For Firmware Version 6, this register contains most of the quarter cycle period data necessary to estimate acceleration. Specifically, the upper 12 bits contains the upper 12 bits of the most recent quarter cycle period (Q1; the lower 8 bits are in the Encoder Velocity (DT) register) and the lower 20 bits contain the previous quarter cycle period (Q5).

For Firmware Version 7+, this register contains only the 24 bits of the current quarter cycle period (Q1) and the previous quarter cycle period (Q5) is available in Encoder Accel Q5.

See the Encoder Velocity section for more information.

Offset 8: Digital Output Control

For Firmware Version 5+, this writes the DOUT control register to set the digital output mode (e.g., PWM, one-shot (pulse), general out). The modes are as follows:

Mode Setting
General DOUT high_time = low_time = 0
Pulse high for DT high_time = DT, low_time = 0
Pulse low for DT high_time = 0, low_time = DT
PWM mode high_time = DTH, low_time = DTL (period = DTH+DTL)

Counts are specified relative to the FPGA sysclk, which is 49.152 MHz. Thus, 1 count is approximately 20 nsec. The maximum 16-bit unsigned value, 65535, corresponds to about 1.33 msec.

Because the digital outputs are inverted in hardware, the convention is that the most significant 16-bits specify the low time and the least significant 16-bits specify the high time.

Note that regardless of the mode, writing to the digital output (DOUT, Global Register 6) will cause it to change to the new value. It will also reset the timer. For example, if we set the control register to pulse high for 100 clocks, but then set DOUT to 1 after 50 clocks, it will stay high for a total of 150 clocks. Writing to the control register also resets the time, so the same behavior would occur if we write to the control register after 50 clocks (assuming we do not also change the high_time).

For the one-shot modes, writing the digital output control will cause the digital output to transition to the inactive state. For example, setting high_time to 1000 and low_time to 0 will have no effect on the digital output if it is already low. If the digital output is high, then the above command will cause the digital output to remain high for 1000 counts and then transition low and remain low. Subsequently, setting the digital output high (via writing to Global Register 6) will cause the digital output to transition high, remain there for 1000 counts, and then transition low (i.e., a positive pulse of 1000 counts duration).

For the PWM mode (high time and low time both non-zero), writing to this register will immediately start PWM mode.

Offset 9: Encoder Accel Q5

Starting with Firmware Version 7, this register provides the previous quarter cycle period (Q5) as a 24-bit number.

See the Encoder Velocity section for more information.

Offset 10: Encoder Running Counter

Starting with Firmware Version 7, this register contains the value of the running counter, which provides the amount of time that has elapsed since the last measured encoder period.

See the Encoder Velocity section for more information.

Offset 11: Motor Config

Starting with Firmware Version 8, this register contains the motor configuration for the QLA and DQLA. It is not implemented in the DRAC firmware, but the AmpIO library returns a value with bits 25 and 24 set to indicate that voltage and current control are both available.

Motor Config Register Read

31-26 25 24 23-16 15-0
unused (0) volt-avail (1) cur-avail (1) amp-delay cur-limit

Motor Config Register Write

31-30 29-26 25 24 23-16 15-0
reserved (0) unused (0) delay-set (1) lim-set (1) amp-delay cur-limit

Motor Config Definitions

The volt-avail bit (read-only) indicates whether the amplifier supports motor voltage control (1 for QLA 1.5+)

The cur-avail bit (read-only) indicates whether the amplifier supports motor current control (always 1 for QLA)

The amp-delay bits (read-write) specify the delay (resolution of 20.83 us) between enabling the follower and leader OPA549 op amps. This is only relevant for QLA 1.5+, because prior versions of the QLA permanently enabled the follower op amp to avoid transients during power up. If the delay is too short, these transients will cause the robot motors to jerk during startup. The default delay value is 120, which is 2.5 ms. The delay-set bit (write-only) must be set to write a new value to amp-delay.

The cur-limit bits (read-write) specify the motor current limit, which is used when the QLA is in voltage control mode (QLA 1.5+). The default motor current limit is 0x0418, which is about 200 mA. The lim-set bit (write-only) must be set to write a new value to cur-limit. In addition, cur-limit must always be positive, so the most significant bit is set to 0 in the firmware (i.e., the valid range is 0x0000 to 0x7fff).

Offset 12: Motor Status

Starting with Firmware Version 8, this register contains the motor status. The format is:

31-30 29 28 27-24 23-21 20 19-16 15-0
unused (0) amp status (1) requested (1) control mode unused (0) cur_ctrl fault code DAC output

The requested bit indicates that the FPGA has accepted the request from the host PC (e.g., via the DAC command register) to enable the motor amplifier. Note that the FPGA may ignore the request due to various interlocks; for example, if the board power is not yet enabled. The amp status bit indicates whether the amplifier is enabled (1) or disabled (0).

The control mode reflects the control mode set via Offset 1. The default value is 0 (current control).

The cur_ctrl bit is used for QLA 1.5+ to indicate whether the amplifier is configured for current control with analog motor current feedback (1), or for voltage control (0).

The fault code has different values for QLA/DQLA and dRAC. For QLA/DQLA, the following bitmask is defined:

Bit Meaning
19 1 -> error setting current control output (QLA 1.5+)
18 1 -> error disabling follower op amp (QLA 1.5+)
17 1 -> disabled due to motor current safety check
16 1 -> amplifier fault (e.g., thermal shutdown)

For dRAC, the fault codes are interpreted as unsigned int. If multiple faults happen at the same time, it will report the smallest fault code.

Fault code Meaning
0 No fault
1 ADC saturated. Possible overcurrent or ADC failure.
2 Current deviated too much from setpoint.
3 Overcurrent shutdown reported by DRV8432.
4 Overtemperature shutdown reported by DRV8432.

6. Encoder Velocity

There are two basic methods to measure velocity using an incremental encoder: (1) measure the time between consecutive encoder edges (DT method), and (2) measure the number of encoder counts within a fixed time period. There are also many variations that combine these methods. Each of these methods has limitations, however. The DT method works well at low encoder frequencies, but has poor resolution at high frequencies because the time between pulses is short. Conversely, the DP method works well at high frequencies, but has poor resolution at low frequencies because the number of pulses in a given time period is small. In terms of practical implementation, it is also important to consider that the DT method will overflow at very low encoder frequencies and the DP method will overflow at very high frequencies.

All versions of firmware provide a measurement using the DT method, although implementation details differ, as described in Encoder Velocity (DT). Early versions of the firmware (up to Version 5) also provided a measurement of the number of encoder counts within a fixed time period, as described in Encoder Velocity (DP), but this was never used by the higher-level software and was removed in firmware Version 6 and replaced by the Encoder Running Counter in firmware Version 7.

One issue for the velocity estimation method is that the reported velocity was actually measured when the last encoder edge occurred, and thus there can be significant time delay in the measurement, especially for low-resolution encoders. Starting with Firmware Version 6, a solution was implemented to compensate for this delay by also estimating the acceleration and updating the velocity based on the acceleration over the estimated time delay. Details of the method are provided in the following paper:

J.Y. Wu, Z. Chen, A. Deguet, P. Kazanzides, "FPGA-Based Velocity Estimation for Control of Robots with Low-Resolution Encoders", IEEE/RSJ Intl. Conf. on Intelligent Robots and Systems (IROS), pp. 6384-6389, Oct. 2018.

Essentially, there are two sources of delay: (1) the measured velocity can be assumed to have occurred at the midpoint (in time) between the two encoder edges, and (2) the time that has elaspsed since the last encoder edge. If S is the last measured period, T is the time since the last edge, and a is the estimated acceleration, the velocity can be estimated by:

V = 4/S + a (S/2 + T)

Firmware Versions 1-5 provide no method for measuring acceleration and thus the velocity is based on the first term above. Firmware Version 6 provides quarter-cycle periods to estimate the acceleration, but does not provide the elapsed time (T), so the above equation is used with T=0. Firmware Version 7+ provides all necessary information for the above equation.

For Firmware Version 6+, the acceleration is estimated from the backward difference between the two most recent full-cycle velocity measurements. This is equivalent to the difference between the most recent quarter-cycle period (Q1) and the quarter-cycle period that occurred four cycles earlier (Q5). Note that a full-cycle measurement is from one encoder edge to the next edge of the same type, whereas a quarter-cycle measurement is from one encoder edge to the next encoder edge. Details are provided in the above paper.

7. PROM 25AA128

7.1 About

The 25AA128 is a 128 kb PROM installed on the companion board (QLA or dRAC) with a page size of 64 bytes. The DQLA interfaces to two QLAs, so it uses channels 1 and 2 to specify which PROM to access (the QLA and dRAC can use channel 0). The channel number is specified in address bits 7-4. The PROM supports a list of standard commands:

Command Description
8'h03 Read
8'h02 Write
8'h04 Write Disable
8'h06 Write Enable
8'h05 Read STATUS register
8'h01 Write STATUS register

Also to support block read and write, we extended the commands

Command Description
8'hFE Read block
8'hFF Write block

7.2 Sending Commands

To send a command to the PROM, write data to 0x3000. See the following examples:

# Write Enable, highest 8-bits is command
./quad1394 0x3000 0x06000000  

# Write Disable, highest 8-bits is command
./quad1394 0x3000 0x04000000  

# Read Status, highest 8-bits is command
./quad1394 0x3000 0x05000000    # send command
./quad1394 0x3002    # read result back 

# Write Status
./quad1394 0x3000 0x06000000  # enable write
./quad1394 0x3000 0x01800000  # 0x01 command 0x80 status 

# Read byte, 0x03 command 0x0010 address 
./quad1394 0x3000 0x03001000

# Write byte 
./quad1394 0x3000 0x06000000  # enable write
./quad1394 0x3000 0x020010AA  # write 0xAA to address 0x0010

7.3 Block Read & Write

A 16 quadlets (64 bytes) buffer is allocated in the FPGA and can be accessed at address 0x3100-0x310F. To program a block of data, for example a page (64-bytes), into the PROM, you need to do the following things:

# 1 Block write data from the data   
./block1394 0x3100 16 0x0100 0x0200 ..... 0x1000 

# 2 Trigger block write
./quad1394 0x3100 0xFF0000F  # last 8-bits is NumOfQuad - 1

To read a block of data from the PROM:

# 1 Trigger block read   
./quad1394 0x3000 0xFE00000F  # last 8-bits is NumOfQuad - 1

# 2 Block read data from the data   
./block1394 0x3100 16

7.4 Sample C++ Code

// Address
AmpIO_UInt16 addr = 0x0000;

// Write Test data
AmpIO_UInt8 wdata = 0xA3;  // test
Board.PromWriteByte25AA128(addr,wdata);

// Read Back
AmpIO_UInt8 rdata;
Board.PromReadByte25AA128(addr, rdata);

Reference

Firewire System Architecture Second Edition IEEE 1394a

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