Resolve HWDT Reset with core_esp8266_vm

[mhightower83]

With the newer GCC compiler (after tag 3.0.2), example virtualmem was crashing with an HWDT reset. Reordered some SPI register set lines in spi_init(). New ordering was based on SPIClass::begin in SPI.cpp.

Someone with a deeper understanding of these SPI registers should review my changes.

This change may resolve issues described in

• 23LC1024 SPI RAM Usage Guidance #9010

Addendum:
I have only tested with the 8M w/256K Heap External 64 MBit PSRAM build option.

[mcspr]

Memory barrier is needed? asm comparison would be more apparent what reordered where

[mhightower83]

Extracted and trimmed old source code

void spi_init(spi_regs *spi1)
{
  spi1->spi_cmd = 0;
  GPMUX &= ~(1 << 9);
  spi1->spi_clock = spi_clkval;
  spi1->spi_ctrl = 0 ; // MSB first + plain SPI mode
  spi1->spi_ctrl1 = 0; // undocumented, clear for safety?
  spi1->spi_ctrl2 = 0; // No add'l delays on signals
  spi1->spi_user2 = 0; // No insn or insn_bits to set
}

Failing build - with compiler from the current master

00000000 <spi_init-0x4>:
   0:   00 08 00 60

00000004 <spi_init>:
   4:   090c                    movi.n  a9, 0
   6:   fffeb1                  l32r    a11, 0 <spi_init-0x4>
                        6: R_XTENSA_SLOT0_OP    .text.spi_init
   9:   0020c0                  memw
   c:   0299                    s32i.n  a9, a2, 0
   e:   0020c0                  memw
  11:   0ba8                    l32i.n  a10, a11, 0
  13:   ffad72                  movi    a7, 0xfffffdff
  16:   10aa70                  and     a10, a10, a7
  19:   0020c0                  memw
  1c:   0ba9                    s32i.n  a10, a11, 0
  1e:   1a0c                    movi.n  a10, 1
  20:   10daa2                  addmi   a10, a10, 0x1000
> 23:   62a9                    s32i.n  a10, a2, 24
> 25:   2299                    s32i.n  a9, a2, 8
  27:   3299                    s32i.n  a9, a2, 12
  29:   5299                    s32i.n  a9, a2, 20
  2b:   9299                    s32i.n  a9, a2, 36
  2d:   f00d                    ret.n

Working build - with compiler from Release 3.0.2

00000000 <spi_init-0x8>:
   0:   00 08 00 60
   4:   01 10 00 00

00000008 <spi_init>:
   8:   030c                    movi.n  a3, 0
   a:   fffd51                  l32r    a5, 0 <spi_init-0x8>
                        a: R_XTENSA_SLOT0_OP    .text.spi_init
   d:   0020c0                  memw
  10:   0239                    s32i.n  a3, a2, 0
  12:   0020c0                  memw
  15:   0548                    l32i.n  a4, a5, 0
  17:   ffad62                  movi    a6, 0xfffffdff
  1a:   104460                  and     a4, a4, a6
  1d:   0020c0                  memw
  20:   0549                    s32i.n  a4, a5, 0
  22:   fff841                  l32r    a4, 4 <spi_init-0x4>
                        22: R_XTENSA_SLOT0_OP   .text.spi_init+0x4
> 25:   2239                    s32i.n  a3, a2, 8
> 27:   6249                    s32i.n  a4, a2, 24
  29:   3239                    s32i.n  a3, a2, 12
  2b:   5239                    s32i.n  a3, a2, 20
  2d:   9239                    s32i.n  a3, a2, 36
  2f:   f00d  

The old compiler reordered instructions such that spi1->spi_ctrl = 0; was performed before spi1->spi_clock = spi_clkval;. Which matches with that in SPIClass::begin from SPI.cpp. I should add a "memory barrier" after spi1->spi_ctrl to my changes.