Skip to content
@efabless

Efabless

Pinned Loading

  1. caravel_user_project caravel_user_project Public template

    https://caravel-user-project.readthedocs.io

    Verilog 193 346

  2. caravel_user_project_analog caravel_user_project_analog Public template

    Verilog 46 94

  3. mpw_precheck mpw_precheck Public

    Python 36 26

  4. caravel caravel Public

    Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

    Verilog 316 74

  5. caravel_board caravel_board Public

    C 33 45

  6. frigate-os frigate-os Public

    Verilog 5

Repositories

Showing 10 of 230 repositories
  • efabless/frigate_user_project’s past year of commit activity
    Verilog 0 2 0 0 Updated Feb 28, 2025
  • efabless/timing-scripts’s past year of commit activity
    Python 0 3 3 0 Updated Feb 28, 2025
  • IHP-Open-PDK Public Forked from IHP-GmbH/IHP-Open-PDK

    130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

    efabless/IHP-Open-PDK’s past year of commit activity
    HTML 1 Apache-2.0 75 1 0 Updated Feb 28, 2025
  • sky130_ef_ip__simple_por Public

    Simple PoR based on an RC filter

    efabless/sky130_ef_ip__simple_por’s past year of commit activity
    Shell 0 Apache-2.0 3 0 0 Updated Feb 26, 2025
  • sky130_ef_ip__adc3v_12bit Public Forked from RTimothyEdwards/sky130_ef_ip__adc3v_12bit

    12-bit ADC using other analog component repositories for the sample & hold, DAC, and comparator.

    efabless/sky130_ef_ip__adc3v_12bit’s past year of commit activity
    Verilog 0 Apache-2.0 5 0 0 Updated Feb 26, 2025
  • sky130_ef_ip__rdac3v_8bit Public Forked from RTimothyEdwards/sky130_ef_ip__rdac3v_8bit

    8-bit resistor ladder DAC with 3.3V output range

    efabless/sky130_ef_ip__rdac3v_8bit’s past year of commit activity
    MATLAB 0 Apache-2.0 4 0 0 Updated Feb 26, 2025
  • openlane-metrics Public

    Repository to store metric results for OpenLane 2.0.0+

    efabless/openlane-metrics’s past year of commit activity
    0 3 0 0 Updated Feb 26, 2025
  • caravel Public

    Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

    efabless/caravel’s past year of commit activity
    Verilog 316 Apache-2.0 74 96 5 Updated Feb 26, 2025
  • openlane2 Public

    The next generation of OpenLane, rewritten from scratch with a modular architecture

    efabless/openlane2’s past year of commit activity
    Python 272 Apache-2.0 54 85 (1 issue needs help) 9 Updated Feb 26, 2025
  • openlane2-step-unit-tests Public

    Step-specific Unit Tests for OpenLane 2.0.0+

    efabless/openlane2-step-unit-tests’s past year of commit activity
    Verilog 0 Apache-2.0 4 0 1 Updated Feb 26, 2025