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Draft PR - Don't merge
As mentioned in #796 , the ADC code requires a re-write in order to make it compatible with Clock V2 API, and to give it an async API.
This Draft PR will track progress I'm making towards this goal.
I've so far created a settings builder type that should be compatible with both 21 and 51 series chips, it allows the user to configure more parameters on how the ADC will sample its data (Along with some good defaults). This is required since due to Clock V2, the ADC clock might not be running at 48Mhz, meaning there is no way to assume the actual sample rate of the ADC at the HAL level, therefore this settings builder also has a
calculate_sps
method so that the user can get an estimated sample rate of the ADC with their desired settings.