Fix mangling of opcodes from SPV_KHR_bit_instructions in SPV-IR (Khro…

…nosGroup#1869)
aratajew · Mar 9, 2023 · c56dc11 · c56dc11
1 parent 759f76b
commit c56dc11
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Showing 2 changed files with 17 additions and 6 deletions.
diff --git a/lib/SPIRV/SPIRVUtil.cpp b/lib/SPIRV/SPIRVUtil.cpp
@@ -2035,6 +2035,7 @@ class SPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
     case OpGroupNonUniformBallotFindMSB:
       addUnsignedArg(1);
       break;
+    case OpBitFieldSExtract:
     case OpGroupNonUniformBallotBitExtract:
       addUnsignedArg(1);
       addUnsignedArg(2);
@@ -2055,6 +2056,7 @@ class SPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
     case OpGroupNonUniformLogicalXor:
       addUnsignedArg(3);
       break;
+    case OpBitFieldInsert:
     case OpGroupNonUniformUMax:
     case OpGroupNonUniformUMin:
       addUnsignedArg(2);
@@ -2105,6 +2107,7 @@ class SPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
     case OpSubgroupAvcImeSetSingleReferenceINTEL:
       addUnsignedArg(1);
       break;
+    case OpBitFieldUExtract:
     case OpSubgroupAvcImeInitializeINTEL:
     case OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL:
     case OpSubgroupAvcSicSetIntraLumaModeCostFunctionINTEL:

diff --git a/test/transcoding/cl_khr_extended_bit_ops.cl b/test/transcoding/cl_khr_extended_bit_ops.cl
@@ -3,6 +3,8 @@
 // RUN: llvm-spirv %t.bc --spirv-ext=+SPV_KHR_bit_instructions -o %t.spv
 // RUN: llvm-spirv -r %t.spv -o %t.rev.bc
 // RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+// RUN: llvm-spirv -r --spirv-target-env=SPV-IR %t.spv -o %t.rev.bc
+// RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-SPV-IR
 
 // TODO: remove prototypes once bit op builtins are available in clang.
 #define __ovld __attribute__((overloadable))
@@ -18,7 +20,8 @@ ulong4 __ovld bit_reverse(ulong4);
 // CHECK-SPIRV: Extension "SPV_KHR_bit_instructions"
 
 // CHECK-LLVM-LABEL: @testInsert
-// CHECK-LLVM: call spir_func <2 x i32> @_Z15bitfield_insertDv2_iS_jj
+// CHECK-LLVM: call spir_func <2 x i32> @_Z15bitfield_insertDv2_iS_jj(
+// CHECK-SPV-IR: call spir_func <2 x i32> @_Z22__spirv_BitFieldInsertDv2_iS_jj(
 // CHECK-SPIRV: Function
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[insbase:[0-9]+]]
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[insins:[0-9]+]]
@@ -28,8 +31,10 @@ kernel void testInsert(int2 b, int2 i, global int2 *res) {
 }
 
 // CHECK-LLVM-LABEL: @testExtractS
-// CHECK-LLVM: call spir_func i16 @_Z23bitfield_extract_signedsjj
-// CHECK-LLVM: call spir_func i16 @_Z23bitfield_extract_signedsjj
+// CHECK-LLVM: call spir_func i16 @_Z23bitfield_extract_signedsjj(
+// CHECK-LLVM: call spir_func i16 @_Z23bitfield_extract_signedsjj(
+// CHECK-SPV-IR: call spir_func i16 @_Z24__spirv_BitFieldSExtractsjj(
+// CHECK-SPV-IR: call spir_func i16 @_Z24__spirv_BitFieldSExtractsjj(
 // CHECK-SPIRV: Function
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[sextrbase:[0-9]+]]
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[sextrbaseu:[0-9]+]]
@@ -41,8 +46,10 @@ kernel void testExtractS(short b, ushort bu, global short *res) {
 }
 
 // CHECK-LLVM-LABEL: @testExtractU
-// CHECK-LLVM: call spir_func <8 x i8> @_Z25bitfield_extract_unsignedDv8_cjj
-// CHECK-LLVM: call spir_func <8 x i8> @_Z25bitfield_extract_unsignedDv8_cjj
+// CHECK-LLVM: call spir_func <8 x i8> @_Z25bitfield_extract_unsignedDv8_cjj(
+// CHECK-LLVM: call spir_func <8 x i8> @_Z25bitfield_extract_unsignedDv8_cjj(
+// CHECK-SPV-IR: call spir_func <8 x i8> @_Z24__spirv_BitFieldUExtractDv8_hjj(
+// CHECK-SPV-IR: call spir_func <8 x i8> @_Z24__spirv_BitFieldUExtractDv8_hjj(
 // CHECK-SPIRV: Function
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[uextrbase:[0-9]+]]
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[uextrbaseu:[0-9]+]]
@@ -54,7 +61,8 @@ kernel void testExtractU(char8 b, uchar8 bu, global uchar8 *res) {
 }
 
 // CHECK-LLVM-LABEL: @testBitReverse
-// CHECK-LLVM: call <4 x i64> @llvm.bitreverse.v4i64
+// CHECK-LLVM: call <4 x i64> @llvm.bitreverse.v4i64(
+// CHECK-SPV-IR: call <4 x i64> @llvm.bitreverse.v4i64(
 // CHECK-SPIRV: Function
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[revbase:[0-9]+]]
 // CHECK-SPIRV: BitReverse {{[0-9]+}} {{[0-9]+}} [[revbase]]