Improve architecture compliance of debug facilities #435
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CIABR (Completed Instruction Address Breakpoint Register) is an SPR that contains an instruction address. When the instruction at that address completes, the CPU takes a Trace interrupt before executing the next instruction (provided the instruction doesn't cause some other interrupt and isn't an rfid, hrfid or rfscv instruction). Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
When an alignment interrupt was being generated, loadstore1 was setting the l_out.valid signal in one cycle and l_out.interrupt in the next, for the same instruction. This meant that the offending instruction completed and the interrupt was applied to the next instruction, meaning that SRR0 ended up pointing to the following instruction. To fix this, when an access causing an alignment interrupt is going into r2, we set r2.busy for one cycle and set r2.one_cycle to 0 so that the complete signal doesn't get asserted. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
…rrupt The tests that intentionally generate alignment interrupts now also check that SRR0 is pointing to a l*arx or st*cx instruction. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This arranges for SIAR and SDAR to be set when a trace interrupt is triggered by a non-zero setting of the MSR[TE] field. According to the ISA, SIAR should be set to the address of the instruction and SDAR should be set to the effective address of its storage operand if any. This also fixes setting of SDAR by the PMU when an alert occurs; previously it was always just set to zero. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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This implements the DAWR0, DAWRX0, DAWR1, and DAWRX1 registers, which provide the ability to set watchpoints on two ranges of data addresses and take an interrupt when an access is made to either range. The address comparisons are done in loadstore1 in the second cycle (doing it in the first cycle turned out to have poor timing). If a match is detected, a signal is sent to the dcache which causes the access to fail and generate an error signal back to loadstore1, in much the same way that a protection violation would, whereupon a data storage interrupt is generated. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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This implements debug facilities - an instruction breakpoint register (CIABR) and two data watchpoints (DAWR[X]{0,1}).
It also fixes the setting of SIAR and SDAR on trace interrupts.