M2k: prepare for alpha - v0.20
Changelog:
065a6be legal_info_html.sh : Add BSD license, and tweak output to make it look like the other files on the mass storage device.
ce36d37 Makefile: Vivado use 2017.4
7ce2ee4 Makefile: Auto-generate LICENSE file
Submodule linux 7fbbe98..105835a:
> iio: logic: m2k-fabric: Add support for DONE LED Overwrite (RevC)
Submodule buildroot a8fcddf..f87e89f:
> html doc pages: Add placeholders & requests for translations which don't exist yet
> html doc pages: add link to license at top, and fix locations of files which don't have translations yet.
> style.css: Add a box with a border around it for the license
> Merge pull request #4 from analogdevicesinc/buildroot-mtools
> html doc pages: Add placeholders & requests for translations which don't exist yet
> html doc pages: add link to license at top, and fix locations of files which don't have translations yet.
> style.css: Add a box with a border around it for the license
> package/libiio: Bump to Version 0.15
> Merge pull request #3 from analogdevicesinc/sidekiq-z2-support
> board/m2k/genimage-msd.cfg: Use auto-generated License file
> board/m2k/msd/.gitignore: Add ignore for autogenerated LICENSE file
> board/pluto/busybox-1.25.0.config: Update config for busybox-1.27.2
> Merge remote-tracking branch 'mainline/2018.02.x' into test-update
> board/pluto/genimage-msd.cfg: Use auto-generated License file
> board/m2k/m2k-calib.ini: Add default (none calibration file)
Submodule u-boot-xlnx efdb9e8..73aff3d:
> Merge pull request #1 from analogdevicesinc/sidekiq-z2-support
Submodule hdl 944edeb...3cf33db:
> axi_dmac: Fix bus resize block reset
> Renamed ad9379 to adrv9009
> adrv9379:zcu102: Update to new revision of the board
> adrv9379:zcu102: Move to FMC1
> adrv9379:zcu102: Cleanup constraints
> adrv9379:zcu102: Fix constraints, from ZCU102 rev B to ZCU102 rev D
> adrv9379:ZCU102: Initial commit
> axi_dmac: Limit MAX_BYTES_PER_BURST to maximum supported value
> axi_dmac: axi_dmac_hw.tcl: Fix indention
> axi_dmac: Prevent destination AXI burst length truncation
> adi_ip.tcl: reorder synthesis files in the file group
> Reviewed pinout of ZCU102 projects. fmcomms5 pin gpio_ad5355_lock location changed
> axi_ad9162: Infer clock signal for tx_clk port
> axi_dmac: adding missing dependency for Intel flow
> axi_dmac: removed harmful SDC constraint
> axi_dmac: AXI3 support on Intel qsys
> fmcjesdadc1:a10: Move block design into feature branch
> daq3: Connect the DAC data underflow
> daq2: Connect the DAC data underflow
> fmcomms5: Connect the DAC data underflow
> fmcomms7: Move project to a feature branch
> usdrx1: Move project to a feature branch
> fmcomms2:pr: Move project to a feature branch
> fmcomms11: Move project to a feature branch
> fmcjesdadc1:altera: Move projects to a feature branch
> daq1: Move project to a feature branch
> usrpe31x: Delete deprecated project
> adrv9364z7020:ccusb: Delete deprecated project
> adrv9361z7035:ccusb: Delete deprecated project
> adrv9361z7035:ccpci: Delete deprecated project
> adv7511:kcu105: Delete deprecated project
> adv7511:vc707: Delete deprecated project
> adv7511:kc705: Delete deprecated project
> ad_sysref_gen: Fix quartus warnings
> ad_datafmt: Fix Quartus warnings
> util_dacfifo: Fix Quartus warnings
> quiet.mk: Fix newline generation in error message
> de10: license: Fix a spelling mistake
> axi_dmac: Disable 2D transfer support by default
> axi_dmac: Remove unused pause signal from address generator
> axi_dmac: Fix some indentation errors
> jesd204: Update testbench with the new file names
> jesd204: Fix file names
> avl_dacfifo: Fix 'blocking statement in always block' issue
> avl_dacfifo: Delete unused files
> library: Remove empty constraint files
> Add quiet mode to the Makefile system
> axi_ad9144: Infer clock signal
> axi_ad9250: Infer clock signals
> Move Altera IP core dependency tracking to library Makefiles
> library: Track additional file types as dependency in Makefile
> axi_dmac_ip.tcl: Add include files to file list
> util_dacfifo: Infer clock and reset signals
> axi_adcfifo: Infer clock and reset signals
> library: Remove unreferenced files from IP file lists
> project-*.mk Update CLEAN targets
> Move Xilinx specific DC filter implementation to library/xilinx/common/
> Makefile: Change IP component dependency to component definition file
> Makefile: Don't create invalid sub-project targets
> Makefile: Simplify sub-project target generation
> Makefile: Update outdated example
> Regenerate library Makefiles using the new shared Makefile include
> Add common library Makefile
> Regenerate project top-level Makefiles
> Add shared project top-level Makefile
> Regenerate project Makefiles using the new shared Makefile includes
> Add common project Makefile for Xilinx projects
> Add common project Makefile for Altera projects
> Remove unused projects/common/Makefile
> adrv9371x: Set up the defualt clock output control
> ad77681evb: Add upscaler to the data path
> adaq7980: Expouse the ADC sampling rate in system_bd.tcl
> util_axis_fifo: instantiate block ram in async mode
> daq3/kcu105: Define transceiver type as Ultrascale
> DE10: Initial commit
> sidekiqz2: Initial commit
> adrv9371: Swap CSN lines to preserve consistency
> ad_dcfilter: Enable output registers in DSP48E1
> adrv9371x:zcu102: Use explicit PACKAGE_PIN definitions for JESD204 lanes and reference clocks
> up_dac_common: Explicitly define boolean parameter as a 1 bit value
> ad_xcvr_rx_if: rx_ip_sof_d register has a width of 4 bits
> avl_dacfifo: Add missing wire declaration
> avl_dacfifo: Delete deprecated false path definition
> license: Fix a spelling mistake
> license: Update old license headers
> axi_hdmi_tx: removed unused registers
> axi_adxcvr: Set the init value of the configuration registers
> util_adxcvr: CPLLPD should be used for reset
> axi_clkgen: Add a parameter to control the clock source options
> adrv9371x:zcu102: Set DEVICE_TYPE to ultrascale
> fmcadc2: Delete redundant settings
> adi_xilinx_msg: eth_avb is not used by our designs
> a10soc: Connect AXI register reset
> util_adxcvr: Don't show reset ports for disabled lanes
> util_[c|u]pack_dsf: clear syntehsis warnings
> util_[w|r]fifo: Reduce synthesis warnings
> up_delay_cntrl: Fix synthesis warnings, no functional changes
> up_[adc|dac]_common: Define the DPR registers only when the interface is enabled
> axi_dmac: fix synthesis warnings
> adrv9379: Fix lane assignment, according to schematic
> common: clean up synthesis warnings
> axi_ad9361: clear synthesis warnings
> adrv936x: Fix Ethernet
> axi_dmac: Added MAX_BYTES_PER_BURST and DISABLE_DEBUG_REGISTERS parameters to Intel IP
> axi_hdmi_tx: Updated .sdc constraints
> axi_hdmi_tx: Use abstract multiplier module supporting both Xilinx and Intel FPGAs
> fmcomms2/zc702: Fix implementation timing issues
> daq3: Add parameters for default xcvr configuration
> daq2/fmcadc4/daq3: Disable the transfer start sync on the ADC DMA
> axi_dmac: In SDP mode REGCEB is connected to GND
> axi_ad7616: Add missing port to instantiation
> spi_engine:axi_spi_engine: Add missing port to instantiations
> axi_ad9963: Fix port dependency definition
> ad738x_zed: Fix SCLK's pin assignment
> ad738x: Add system variables for configuration
> ad_tdd_control: Fix the tdd_burst_counter implementation
> ad7134_fmc: Initial commit
> util_axis_upscale: Initial commit
> spi_engine: Add support for 8 SDI lines
> util_pulse_gen: Use equal-to for counter reset
> up_[adc|dac]_common: DRP_DISABLE should be boolean
> constraints: up_xfer_cntrl and up_xfer_status have its own constraints
> ad6676evb: Fix RX_DFE_LPM_CFG parameter, as the design is used in DFE mode
> fmcadc5: Fix RXCDR_CFG parameter
> fmcadc5: Remove xcvr configuration options that don't matter
> axi_dacfifo: Rewrote constraints to be more specific
> system_top: Non functional changes in system_tops to reduce warnings
> axi_ad9434: Make adc_enable controllable from the channel register map
> axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
> axi_*: Infer clock and reset signals of an IP
> up_clock_com: Fix the false path definitions for CDCs
> jesd_rst_gen:constraints: Remove invalid false path definitions
> kc705/vc707/kcu105: Fix axi_spi related critical warning
> axi_adcfifo_constr.xdc: Add missing backslash to command
> axi_ad9162: Fix code alignment, no functional changes
> base:constraint: Setting Configuration Bank Voltage Select
> common/up_* : Make up_rstn synchronous to up_clk
> scripts:adi_project: Update ZCU102 device package and board files
> zcu102:all_projects: Delete required version tcl variable
> scripts:adi_project: Use default strategies for synth and impl
> scripts:adi_ip: Update web address format
> scripts: Message severity changes on Vivado
> scripts: Update tools for the next release
> usb_fx3: Delete unused project
> cftl: Delete unused projects and libraries
> jesd204:tb: Fix the loopback_tb test bench
> README: Remove the Documentation section, it's redundant
> README: General rework and add more embedded links to wiki
> README: A generic README update
> axi_logic_analyzer: Fix push-pull/open-drain selection
> Make: Use $(MAKE) for recursive make commands
> Remove unused Q_OR_I_N parameter from JESD204 ADC cores
> Remove unused IO_DELAY_GROUP parameter from JESD204 ADC cores
> ad6676: Fix OUT_CLK_SEL configuration
> fmcjesdadc1: Fix OUT_CLK_SEL configuration
> fmcjesdadc1: Remove wire that is a redeclaration of a port
> fmcomms5: Remove wires that are redeclarations of ports
> axi_clkgen: add ultrascale series support
> adrv9371x/kcu105: Use ultrascale type primitives in axi_clkgen IP
> adrv9371x:kcu105: Update transceiver configuration
> adrv9371x: kcu105: Fix transceiver and clock placement
< axi_logic_analyzer: Fix push-pull/open-drain selection
> Merge branch hdl_2017_r1
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
