CPU_project

recording codes of CPU under mips ISA in lecture of computer organization in BUAA2020
here is a brief introduction of each branch:
Project number: content (base_stage)
P0: digital circuits (Logism)
P1: digital circuits focus on state-machine (Verilog)
P2: mips assembly language (Mars)
P3: Single cycle CPU with 9 mips commands (Logism)
P4: Single cycle CPU with 9 mips commands (Verilog)
P5: Pipelined CPU with 11 mips commands (Verilog)
P6: Pipelined CPU with 52 mips commands (Verilog)
P7: Pipelined CPU with interrupt/exception handling supported (Verilog)