Bump Chisel 6.4.0 and Scala 2.13.14 (#202)

OSCPU · Jul 1, 2024 · 52aeba5 · 52aeba5
1 parent ba8347d
commit 52aeba5
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/build.sc b/build.sc
@@ -2,9 +2,9 @@ import mill._, scalalib._
 import coursier.maven.MavenRepository
 
 object ivys {
-  val scala = "2.13.12"
-  val chisel = ivy"org.chipsalliance::chisel:6.3.0"
-  val chiselPlugin = ivy"org.chipsalliance:::chisel-plugin:6.3.0"
+  val scala = "2.13.14"
+  val chisel = ivy"org.chipsalliance::chisel:6.4.0"
+  val chiselPlugin = ivy"org.chipsalliance:::chisel-plugin:6.4.0"
 }
 
 trait CommonModule extends ScalaModule {

diff --git a/difftest b/difftest
+12 −2		.github/workflows/main.yml
+3 −3		README.md
+4 −4		build.sc
+20 −3		src/main/scala/Batch.scala
+6 −1		src/main/scala/Bundles.scala
+37 −8		src/main/scala/Difftest.scala
+54 −37		src/main/scala/Gateway.scala
+2 −2		src/main/scala/Replay.scala
+21 −10		src/main/scala/Squash.scala
+8 −3		src/test/csrc/common/SimJTAG.cpp
+0 −1		src/test/csrc/common/common.h
+5 −0		src/test/csrc/common/remote_bitbang.h
+52 −61		src/test/csrc/difftest/difftest.cpp
+7 −2		src/test/csrc/difftest/difftest.h
+7 −5		src/test/csrc/verilator/emu.cpp
+0 −1		src/test/csrc/verilator/emu.h
+242 −0		src/test/vsrc/vcs/DifftestEndpoint.v
+20 −196		src/test/vsrc/vcs/top.v
+41 −3		vcs.mk
+85 −12		verilator.mk