Merge pull request #896 from NREL-SIIP/rh/add_stab1_parser

Add STAB1 parser
NREL-Sienna · Jun 1, 2022 · adb4bb5 · adb4bb5 · jd-lara · Jun 1, 2022
2 parents ce96ebf + db368c8
commit adb4bb5
Show file tree

Hide file tree

Showing 4 changed files with 11 additions and 5 deletions.
diff --git a/src/PowerSystems.jl b/src/PowerSystems.jl
@@ -125,6 +125,7 @@ export PSS
 export PSSFixed
 export PSSSimple
 export IEEEST
+export STAB1
 
 #Shaft Exports
 export Shaft

diff --git a/src/descriptors/power_system_structs.json b/src/descriptors/power_system_structs.json
@@ -8950,7 +8950,7 @@
         {
           "name": "states",
           "exclude_setter": true,
-          "comment": "The states are:\n\tx_p1: washout filter,\n\tx_p2: T1/T2 lead-lag block, \n\tx_p3: T3/T4 lead-lag block,",
+          "comment": "The states are:\n\tx_p1: washout filter,\n\tx_p2: T1/T3 lead-lag block, \n\tx_p3: T2/T4 lead-lag block,",
           "internal_default": "[:x_p1, :x_p2, :x_p3]",
           "data_type": "Vector{Symbol}"
         },

diff --git a/src/models/generated/STAB1.jl b/src/models/generated/STAB1.jl
@@ -33,8 +33,8 @@ Speed-Sensitive Stabilizing Model
 - `ext::Dict{String, Any}`
 - `states::Vector{Symbol}`: The states are:
 	x_p1: washout filter,
-	x_p2: T1/T2 lead-lag block, 
-	x_p3: T3/T4 lead-lag block,
+	x_p2: T1/T3 lead-lag block, 
+	x_p3: T2/T4 lead-lag block,
 - `n_states::Int`: STAB1 has 3 states
 - `states_types::Vector{StateTypes}`: STAB1 has 3 differential states
 - `internal::InfrastructureSystemsInternal`: power system internal reference, do not modify
@@ -57,8 +57,8 @@ mutable struct STAB1 <: PSS
     ext::Dict{String, Any}
     "The states are:
 	x_p1: washout filter,
-	x_p2: T1/T2 lead-lag block, 
-	x_p3: T3/T4 lead-lag block,"
+	x_p2: T1/T3 lead-lag block, 
+	x_p3: T2/T4 lead-lag block,"
     states::Vector{Symbol}
     "STAB1 has 3 states"
     n_states::Int

diff --git a/src/parsers/psse_dynamic_mapping.yaml b/src/parsers/psse_dynamic_mapping.yaml
@@ -130,6 +130,10 @@ TGOV1DU:
 IEEEST:
 {
   PSS: IEEEST
+},
+STAB1:
+{
+  PSS: STAB1
 }
 }
 
@@ -229,6 +233,7 @@ parameter_mapping:
   TGOV1DU: [1, 2, '(4, 3)', 5, 6, 7, 8, 9, 10],
   #PSSs:
   IEEEST: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, '(17, 16)', 18, 19],
+  STAB1: [1, 2, 3, 4, 5, 6, 7],
 
   ###################
   #### Inverters ####