Skip to content

Commit

Permalink
Arm64: FCVTZS, FCVTZU instructions + tests
Browse files Browse the repository at this point in the history
- let's start testing
  • Loading branch information
MatejKastak committed Mar 1, 2019
1 parent 35b2d35 commit d980328
Show file tree
Hide file tree
Showing 4 changed files with 162 additions and 2 deletions.
23 changes: 23 additions & 0 deletions src/capstone2llvmir/arm64/arm64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2429,6 +2429,29 @@ void Capstone2LlvmIrTranslatorArm64_impl::translateFCvtf(cs_insn* i, cs_arm64* a
}
}

/**
* ARM64_INS_FCVTZS, ARM64_INS_FCVTZU
*/
void Capstone2LlvmIrTranslatorArm64_impl::translateFCvtz(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb)
{
EXPECT_IS_BINARY(i, ai, irb);

op1 = loadOp(ai->operands[1], irb);

switch(i->id)
{
case ARM64_INS_FCVTZU:
op1 = irb.CreateFPToSI(op1, getRegisterType(ai->operands[0].reg));
break;
case ARM64_INS_FCVTZS:
op1 = irb.CreateFPToUI(op1, getRegisterType(ai->operands[0].reg));
break;
default:
throw GenericError("Arm64: translateFCvtz(): Unsupported instruction id");
}
storeOp(ai->operands[0], op1, irb);
}

/**
* ARM64_INS_FDIV
*/
Expand Down
1 change: 1 addition & 0 deletions src/capstone2llvmir/arm64/arm64_impl.h
Original file line number Diff line number Diff line change
Expand Up @@ -214,6 +214,7 @@ class Capstone2LlvmIrTranslatorArm64_impl :
void translateFCsel(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
void translateFCvt(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
void translateFCvtf(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
void translateFCvtz(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
void translateFDiv(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
void translateFMadd(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
void translateFMinMax(cs_insn* i, cs_arm64* ai, llvm::IRBuilder<>& irb);
Expand Down
4 changes: 2 additions & 2 deletions src/capstone2llvmir/arm64/arm64_init.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -513,8 +513,8 @@ Capstone2LlvmIrTranslatorArm64_impl::_i2fm =
{ARM64_INS_FCVTPU, nullptr},
{ARM64_INS_FCVTXN, nullptr},
{ARM64_INS_FCVTXN2, nullptr},
{ARM64_INS_FCVTZS, nullptr},
{ARM64_INS_FCVTZU, nullptr},
{ARM64_INS_FCVTZS, &Capstone2LlvmIrTranslatorArm64_impl::translateFCvtz},
{ARM64_INS_FCVTZU, &Capstone2LlvmIrTranslatorArm64_impl::translateFCvtz},
{ARM64_INS_FDIV, &Capstone2LlvmIrTranslatorArm64_impl::translateFDiv},
{ARM64_INS_FMADD, &Capstone2LlvmIrTranslatorArm64_impl::translateFMadd},
{ARM64_INS_FMAX, &Capstone2LlvmIrTranslatorArm64_impl::translateFMinMax},
Expand Down
136 changes: 136 additions & 0 deletions tests/capstone2llvmir/arm64_tests.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -6895,6 +6895,142 @@ TEST_P(Capstone2LlvmIrTranslatorArm64Tests, ARM64_INS_UCVTF_d_x)
EXPECT_NO_VALUE_CALLED();
}

//
// ARM64_INS_FCVTZS
//

TEST_P(Capstone2LlvmIrTranslatorArm64Tests, ARM64_INS_FCVTZS_w_s)
{
setRegisters({
{ARM64_REG_S1, static_cast<float>(-1.0)},
});

emulate("fcvtzs w0, s1");

EXPECT_JUST_REGISTERS_LOADED({ARM64_REG_S1});
EXPECT_JUST_REGISTERS_STORED({
{ARM64_REG_W0, 0xffffffff},
});
EXPECT_NO_MEMORY_LOADED_STORED();
EXPECT_NO_VALUE_CALLED();
}

TEST_P(Capstone2LlvmIrTranslatorArm64Tests, ARM64_INS_FCVTZS_w_d)
{
setRegisters({
{ARM64_REG_D1, 123.9_f64},
});

emulate("fcvtzs w0, d1");

EXPECT_JUST_REGISTERS_LOADED({ARM64_REG_D1});
EXPECT_JUST_REGISTERS_STORED({
{ARM64_REG_W0, 123},
});
EXPECT_NO_MEMORY_LOADED_STORED();
EXPECT_NO_VALUE_CALLED();
}

TEST_P(Capstone2LlvmIrTranslatorArm64Tests, ARM64_INS_FCVTZS_x_s)
{
setRegisters({
{ARM64_REG_S1, static_cast<float>(-1)},
});

emulate("fcvtzs x0, s1");

EXPECT_JUST_REGISTERS_LOADED({ARM64_REG_S1});
EXPECT_JUST_REGISTERS_STORED({
{ARM64_REG_X0, 0xffffffffffffffff},
});
EXPECT_NO_MEMORY_LOADED_STORED();
EXPECT_NO_VALUE_CALLED();
}

TEST_P(Capstone2LlvmIrTranslatorArm64Tests, ARM64_INS_FCVTZS_x_d)
{
setRegisters({
{ARM64_REG_D1, 123.3_f64},
});

emulate("fcvtzs x0, d1");

EXPECT_JUST_REGISTERS_LOADED({ARM64_REG_D1});
EXPECT_JUST_REGISTERS_STORED({
{ARM64_REG_X0, 123},
});
EXPECT_NO_MEMORY_LOADED_STORED();
EXPECT_NO_VALUE_CALLED();
}

//
// ARM64_INS_FCVTZU
//

TEST_P(Capstone2LlvmIrTranslatorArm64Tests, ARM64_INS_FCVTZU_w_s)
{
setRegisters({
{ARM64_REG_S1, 31232321.0_f32},
});

emulate("fcvtzu w0, s1");

EXPECT_JUST_REGISTERS_LOADED({ARM64_REG_S1});
EXPECT_JUST_REGISTERS_STORED({
{ARM64_REG_W0, 0x1dc9140},
});
EXPECT_NO_MEMORY_LOADED_STORED();
EXPECT_NO_VALUE_CALLED();
}

TEST_P(Capstone2LlvmIrTranslatorArm64Tests, ARM64_INS_FCVTZU_w_d)
{
setRegisters({
{ARM64_REG_D1, 123.5_f64},
});

emulate("fcvtzu w0, d1");

EXPECT_JUST_REGISTERS_LOADED({ARM64_REG_D1});
EXPECT_JUST_REGISTERS_STORED({
{ARM64_REG_W0, 123},
});
EXPECT_NO_MEMORY_LOADED_STORED();
EXPECT_NO_VALUE_CALLED();
}

TEST_P(Capstone2LlvmIrTranslatorArm64Tests, ARM64_INS_FCVTZU_x_s)
{
setRegisters({
{ARM64_REG_S1, 9.22337204e+18_f32},
});

emulate("fcvtzu x0, s1");

EXPECT_JUST_REGISTERS_LOADED({ARM64_REG_S1});
EXPECT_JUST_REGISTERS_STORED({
{ARM64_REG_X0, 0x8000000000000000},
});
EXPECT_NO_MEMORY_LOADED_STORED();
EXPECT_NO_VALUE_CALLED();
}

TEST_P(Capstone2LlvmIrTranslatorArm64Tests, ARM64_INS_FCVTZU_x_d)
{
setRegisters({
{ARM64_REG_D1, 123.0_f64},
});

emulate("fcvtzu x0, d1");

EXPECT_JUST_REGISTERS_LOADED({ARM64_REG_D1});
EXPECT_JUST_REGISTERS_STORED({
{ARM64_REG_X0, 123},
});
EXPECT_NO_MEMORY_LOADED_STORED();
EXPECT_NO_VALUE_CALLED();
}

//
// ARM64_INS_FDIV
//
Expand Down

0 comments on commit d980328

Please sign in to comment.