i#7161: Set bit 4 of the CPSR in the sigframe. #7209
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Bit 4 of the ARM (AArch32) CPSR is RES1, meaning that it is either hardwired to 1 or its value should be preserved. With newer kernels sigreturn generates a SIGSEGV if it sees that this bit is not set in the sigframe. It might be better to preserve the value of this bit throughout DynamoRIO (i#7207) but for now we just set it in the place that seems to matter. Fixes: #7161 Change-Id: I0c39dde5673d8d535d4427e3d150779270c88d2a
derekbruening
approved these changes
Jan 23, 2025
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Bit 4 of the ARM (AArch32) CPSR is RES1, meaning that it is either hardwired to 1 or its value should be preserved. With newer kernels sigreturn generates a SIGSEGV if it sees that this bit is not set in the sigframe. It might be better to preserve the value of this bit throughout DynamoRIO (i#7207) but for now we just set it in the place that seems to matter.
Issue: #7207
Fixes: #7161