ARM: Preserve RES0 and RES1 bit values in CPSR throughout DynamoRIO #7207
Labels
Comments
egrimley-arm
added a commit
that referenced
this issue
Jan 23, 2025
Bit 4 of the ARM (AArch32) CPSR is RES1, meaning that it is either hardwired to 1 or its value should be preserved. With newer kernels sigreturn generates a SIGSEGV if it sees that this bit is not set in the sigframe. It might be better to preserve the value of this bit throughout DynamoRIO (i#7207) but for now we just set it in the place that seems to matter. Issue: #7207 Fixes: #7161
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
On ARM (AArch32) bit 4 of the CPSR is RES1, meaning that it is implementation-defined whether it is hardwired to 1 or its value can be changed, so software should either write 1 to it or preserve its value, with the latter preferred, I think.
With newer kernels, if the
sigreturnsystem call sees a 0 in bit 4 of the CPSR in the sigframe then it generates aSIGSEGV(with the PC taken from the sigframe, apparently, so the segfault seen under GDB can be confusing). It is proposed to fix this (#7161) by setting the bit inmcontext_to_sigcontext. It is likely that a better solution would be to preserve bit 4 throughout DynamoRIO so that all CPSR values have bit 4 set, but that would be a bigger change and may turn out to be a compatibility change.At the same time one might try to ensure that the values of RES0 bits are preserved rather than constantly reset to 0.
Currently the RES0 bits are bits 5, 10-15, 20, 24-26, and the RES1 bits are just bit 4.
The text was updated successfully, but these errors were encountered: