fix EVEX.RXB operands decoding

BeaEngine · Aug 6, 2019 · f0f5844 · f0f5844
1 parent 1356002
commit f0f5844
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Showing 300 changed files with 1,465 additions and 1,446 deletions.
diff --git a/src/Includes/Routines_ModRM.c b/src/Includes/Routines_ModRM.c
@@ -1733,7 +1733,10 @@ size_t __bea_callspec__ interpretVSIBIndex(OPTYPE* pMyOperand, size_t i, PDISASM
   i = printSeparator(pMyOperand, i, pMyDisasm);
 
   if (GV.AddressSize >= 32) {
-    if (GV.EVEX.X == 0) {
+    if (
+        ((GV.EVEX.state == InUsePrefix) && (GV.EVEX.X == 0)) ||
+        ((GV.EVEX.state != InUsePrefix) && (GV.REX.X_ == 0)) 
+      ) {
       index_final = (GV.EVEX.V == 0) ? GV.INDEX_ : GV.INDEX_ + 16;
     }
     else {

diff --git a/src/Includes/instr_set/instructions_list.c b/src/Includes/instr_set/instructions_list.c
@@ -637,12 +637,12 @@ void __bea_callspec__ bound_(PDISASM pMyDisasm)
       GV.EVEX.state = InUsePrefix;
       GV.EVEX.mm = GV.EVEX.P0 & 0x3;           /* P[1:0] */
       GV.EVEX.pp = GV.EVEX.P1 & 0x3;           /* P[9:8] */
-      GV.EVEX.R1 = (GV.EVEX.P0 >> 4) & 0x1;      /* P[4] */
-      GV.EVEX.X = (GV.EVEX.P0 >> 6) & 0x1;      /* P[6] */
-      GV.EVEX.B = (GV.EVEX.P0 >> 5) & 0x1;      /* P[5] */
-      GV.EVEX.R = (GV.EVEX.P0 >> 7) & 0x1;      /* P[5] */
+      GV.EVEX.R1 = ~(GV.EVEX.P0 >> 4) & 0x1;      /* P[4] */
+      GV.EVEX.X = ~(GV.EVEX.P0 >> 6) & 0x1;      /* P[6] */
+      GV.EVEX.B = ~(GV.EVEX.P0 >> 5) & 0x1;      /* P[5] */
+      GV.EVEX.R = ~(GV.EVEX.P0 >> 7) & 0x1;      /* P[5] */
       GV.EVEX.vvvv = (GV.EVEX.P1 >> 3) & 0xF; /* P[14:11] */
-      GV.EVEX.V = (GV.EVEX.P2 >> 3) & 0x1;      /* P[19] */
+      GV.EVEX.V = ~(GV.EVEX.P2 >> 3) & 0x1;      /* P[19] */
       GV.EVEX.aaa = (GV.EVEX.P2) & 0x7;       /* P[18:16] */
       GV.EVEX.W = (GV.EVEX.P1 >> 7) & 0x1;      /* P[15] */
       GV.EVEX.z = (GV.EVEX.P2 >> 7) & 0x1;      /* P[23] */

diff --git a/src/Includes/internal_datas.h b/src/Includes/internal_datas.h
@@ -754,7 +754,7 @@ char RegistersAVX512[32][8] = {
 /* =====================================================
  * opmask registers
  * ===================================================== */
-char RegistersOpmask[16][4] = {
+char RegistersOpmask[32][4] = {
     "k0",
     "k1",
     "k2",
@@ -770,6 +770,22 @@ char RegistersOpmask[16][4] = {
     "k?",
     "k?",
     "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
+    "k?",
     "k?"
 };
 

diff --git a/tests/0f10.py b/tests/0f10.py
@@ -74,7 +74,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x10')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovsd ')
-        assert_equal(myDisasm.infos.repr, 'vmovsd xmm2, xmm15, xmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovsd xmm26, xmm31, xmmword ptr [r8+00000000h]')
 
         # EVEX.LIG.F2.0F.W1 10 /r
         # VMOVSD xmm1 {k1}{z}, m64
@@ -89,7 +89,7 @@ def test(self):
         assert_equal(myDisasm.infos.Reserved_.EVEX.vvvv, 0xF)
         assert_equal(myDisasm.infos.Reserved_.VEX.vvvv, 0xF)
         assert_equal(myDisasm.infos.Reserved_.VEX.pp, 0x3)
-        assert_equal(myDisasm.infos.repr, 'vmovsd xmm2, qword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovsd xmm26, qword ptr [r8+00000000h]')
 
         # F3 0F 10 /r
         # MOVSS xmm1, xmm2
@@ -142,7 +142,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x10')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovss ')
-        assert_equal(myDisasm.infos.repr, 'vmovss xmm4, xmm15, xmm0')
+        assert_equal(myDisasm.infos.repr, 'vmovss xmm28, xmm31, xmm24')
 
         # EVEX.LIG.F3.0F.W0 10 /r
         # VMOVSS xmm1 {k1}{z}, m32
@@ -154,7 +154,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x10')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovss ')
-        assert_equal(myDisasm.infos.repr, 'vmovss xmm2, dword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovss xmm26, dword ptr [r8+00000000h]')
 
         # 66 0F 10 /r
         # MOVUPD xmm1, xmm2/m128
@@ -195,7 +195,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x10')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovupd ')
-        assert_equal(myDisasm.infos.repr, 'vmovupd xmm2, xmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovupd xmm26, xmmword ptr [r8+00000000h]')
 
 
         myEVEX = EVEX('EVEX.128.66.0F.W1')
@@ -207,7 +207,7 @@ def test(self):
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x10')
         assert_equal(myDisasm.infos.Reserved_.EVEX.aaa, 1)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovupd ')
-        assert_equal(myDisasm.infos.repr, 'vmovupd xmm2 {k1}{0}, xmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovupd xmm26 {k1}{0}, xmmword ptr [r8+00000000h]')
 
         myEVEX = EVEX('EVEX.128.66.0F.W1')
         myEVEX.aaa = 1
@@ -219,7 +219,7 @@ def test(self):
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x10')
         assert_equal(myDisasm.infos.Reserved_.EVEX.aaa, 1)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovupd ')
-        assert_equal(myDisasm.infos.repr, 'vmovupd xmm2 {k1}{1}, xmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovupd xmm26 {k1}{1}, xmmword ptr [r8+00000000h]')
 
         # EVEX.256.66.0F.W1 10 /r
         # VMOVUPD ymm1 {k1}{z}, ymm2/m256
@@ -230,7 +230,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x10')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovupd ')
-        assert_equal(myDisasm.infos.repr, 'vmovupd ymm2, ymmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovupd ymm26, ymmword ptr [r8+00000000h]')
 
         # EVEX.512.66.0F.W1 10 /r
         # VMOVUPD zmm1 {k1}{z}, zmm2/m512
@@ -241,7 +241,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x10')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovupd ')
-        assert_equal(myDisasm.infos.repr, 'vmovupd zmm2, zmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovupd zmm26, zmmword ptr [r8+00000000h]')
 
 
         # 0F 10 /r
@@ -283,7 +283,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x10')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovups ')
-        assert_equal(myDisasm.infos.repr, 'vmovups xmm2, xmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovups xmm26, xmmword ptr [r8+00000000h]')
 
         # EVEX.256.0F.W1 10 /r
         # VMOVUPD ymm1 {k1}{z}, ymm2/m256
@@ -294,7 +294,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x10')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovups ')
-        assert_equal(myDisasm.infos.repr, 'vmovups ymm2, ymmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovups ymm26, ymmword ptr [r8+00000000h]')
 
         # EVEX.512.0F.W1 10 /r
         # VMOVUPD zmm1 {k1}{z}, zmm2/m512
@@ -305,4 +305,4 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x10')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovups ')
-        assert_equal(myDisasm.infos.repr, 'vmovups zmm2, zmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovups zmm26, zmmword ptr [r8+00000000h]')
diff --git a/tests/0f11.py b/tests/0f11.py
@@ -74,7 +74,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x11')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovsd ')
-        assert_equal(myDisasm.infos.repr, 'vmovsd xmmword ptr [rax+00000000h], xmm15, xmm2')
+        assert_equal(myDisasm.infos.repr, 'vmovsd xmmword ptr [r8+00000000h], xmm31, xmm26')
 
         # EVEX.LIG.F2.0F.W1 11 /r
         # VMOVSD m64, xmm1 {k1}{z}
@@ -89,7 +89,7 @@ def test(self):
         assert_equal(myDisasm.infos.Reserved_.EVEX.vvvv, 0xF)
         assert_equal(myDisasm.infos.Reserved_.VEX.vvvv, 0xF)
         assert_equal(myDisasm.infos.Reserved_.VEX.pp, 0x3)
-        assert_equal(myDisasm.infos.repr, 'vmovsd qword ptr [rax+00000000h], xmm2')
+        assert_equal(myDisasm.infos.repr, 'vmovsd qword ptr [r8+00000000h], xmm26')
 
         # F3 0F 11 /r
         # MOVSS xmm1, xmm2
@@ -142,7 +142,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x11')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovss ')
-        assert_equal(myDisasm.infos.repr, 'vmovss xmm0, xmm15, xmm4')
+        assert_equal(myDisasm.infos.repr, 'vmovss xmm24, xmm31, xmm28')
 
         # EVEX.LIG.F3.0F.W0 11 /r
         # VMOVSS  m32, xmm1 {k1}{z}
@@ -154,7 +154,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x11')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovss ')
-        assert_equal(myDisasm.infos.repr, 'vmovss dword ptr [rax+00000000h], xmm2')
+        assert_equal(myDisasm.infos.repr, 'vmovss dword ptr [r8+00000000h], xmm26')
 
         # 66 0F 11 /r
         # MOVUPD xmm2/m128, xmm1
@@ -195,7 +195,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x11')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovupd ')
-        assert_equal(myDisasm.infos.repr, 'vmovupd xmmword ptr [rax+00000000h], xmm2')
+        assert_equal(myDisasm.infos.repr, 'vmovupd xmmword ptr [r8+00000000h], xmm26')
 
         # EVEX.256.66.0F.W1 11 /r
         # VMOVUPD ymm2/m256, ymm1 {k1}{z}
@@ -206,7 +206,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x11')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovupd ')
-        assert_equal(myDisasm.infos.repr, 'vmovupd ymmword ptr [rax+00000000h], ymm2')
+        assert_equal(myDisasm.infos.repr, 'vmovupd ymmword ptr [r8+00000000h], ymm26')
 
         # EVEX.512.66.0F.W1 11 /r
         # VMOVUPD zmm2/m512, zmm1 {k1}{z}
@@ -217,7 +217,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x11')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovupd ')
-        assert_equal(myDisasm.infos.repr, 'vmovupd zmmword ptr [rax+00000000h], zmm2')
+        assert_equal(myDisasm.infos.repr, 'vmovupd zmmword ptr [r8+00000000h], zmm26')
 
 
         # 0F 11 /r
@@ -259,7 +259,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x11')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovups ')
-        assert_equal(myDisasm.infos.repr, 'vmovups xmmword ptr [rax+00000000h], xmm2')
+        assert_equal(myDisasm.infos.repr, 'vmovups xmmword ptr [r8+00000000h], xmm26')
 
         # EVEX.256.0F.W1 11 /r
         # VMOVUPD ymm2/m256, ymm1 {k1}{z}
@@ -270,7 +270,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x11')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovups ')
-        assert_equal(myDisasm.infos.repr, 'vmovups ymmword ptr [rax+00000000h], ymm2')
+        assert_equal(myDisasm.infos.repr, 'vmovups ymmword ptr [r8+00000000h], ymm26')
 
         # EVEX.512.0F.W1 11 /r
         # VMOVUPD zmm2/m512, zmm1 {k1}{z}
@@ -281,4 +281,4 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x11')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovups ')
-        assert_equal(myDisasm.infos.repr, 'vmovups zmmword ptr [rax+00000000h], zmm2')
+        assert_equal(myDisasm.infos.repr, 'vmovups zmmword ptr [r8+00000000h], zmm26')
diff --git a/tests/0f12.py b/tests/0f12.py
@@ -51,7 +51,7 @@ def test(self):
         myDisasm.read()
         assert_equal(myDisasm.infos.Instruction.Opcode, 0x12)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovhlps ')
-        assert_equal(myDisasm.infos.repr, 'vmovhlps xmm4, xmm15, xmm0')
+        assert_equal(myDisasm.infos.repr, 'vmovhlps xmm28, xmm31, xmm24')
 
         # NP 0F 12 /r
         # MOVLPS xmm1, m64
@@ -83,7 +83,7 @@ def test(self):
         myDisasm.read()
         assert_equal(myDisasm.infos.Instruction.Opcode, 0x12)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovlps ')
-        assert_equal(myDisasm.infos.repr, 'vmovlps xmm2, xmm15, qword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovlps xmm26, xmm31, qword ptr [r8+00000000h]')
 
         # 66 0F 12 /r
         # MOVLPD xmm1, m64
@@ -115,7 +115,7 @@ def test(self):
         myDisasm.read()
         assert_equal(myDisasm.infos.Instruction.Opcode, 0x12)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovlpd ')
-        assert_equal(myDisasm.infos.repr, 'vmovlpd xmm2, xmm15, qword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovlpd xmm26, xmm31, qword ptr [r8+00000000h]')
 
         # F2 0F 12 /r
         # MOVDDUP xmm1, xmm2/m64
@@ -158,7 +158,7 @@ def test(self):
         myDisasm.read()
         assert_equal(myDisasm.infos.Instruction.Opcode, 0x12)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovddup ')
-        assert_equal(myDisasm.infos.repr, 'vmovddup xmm2, qword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovddup xmm26, qword ptr [r8+00000000h]')
 
         # EVEX.256.F2.0F.W1 12 /r
         # VMOVDDUP ymm1 {k1}{z}, ymm2/m256
@@ -169,7 +169,7 @@ def test(self):
         myDisasm.read()
         assert_equal(myDisasm.infos.Instruction.Opcode, 0x12)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovddup ')
-        assert_equal(myDisasm.infos.repr, 'vmovddup ymm2, ymmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovddup ymm26, ymmword ptr [r8+00000000h]')
 
         # EVEX.512.F2.0F.W1 12 /r
         # VMOVDDUP zmm1 {k1}{z}, zmm2/m512
@@ -180,7 +180,7 @@ def test(self):
         myDisasm.read()
         assert_equal(myDisasm.infos.Instruction.Opcode, 0x12)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovddup ')
-        assert_equal(myDisasm.infos.repr, 'vmovddup zmm2, zmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovddup zmm26, zmmword ptr [r8+00000000h]')
 
         # F3 0F 12 /r
         # MOVSLDUP xmm1, xmm2/m128
@@ -223,7 +223,7 @@ def test(self):
         myDisasm.read()
         assert_equal(myDisasm.infos.Instruction.Opcode, 0x12)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovsldup ')
-        assert_equal(myDisasm.infos.repr, 'vmovsldup xmm2, xmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovsldup xmm26, xmmword ptr [r8+00000000h]')
 
         # EVEX.256.F3.0F.W0 12 /r
         # VMOVSLDUP ymm1 {k1}{z}, ymm2/m256
@@ -234,7 +234,7 @@ def test(self):
         myDisasm.read()
         assert_equal(myDisasm.infos.Instruction.Opcode, 0x12)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovsldup ')
-        assert_equal(myDisasm.infos.repr, 'vmovsldup ymm2, ymmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovsldup ymm26, ymmword ptr [r8+00000000h]')
 
         # EVEX.512.F3.0F.W0 12 /r
         # VMOVSLDUP zmm1 {k1}{z}, zmm2/m512
@@ -245,4 +245,4 @@ def test(self):
         myDisasm.read()
         assert_equal(myDisasm.infos.Instruction.Opcode, 0x12)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovsldup ')
-        assert_equal(myDisasm.infos.repr, 'vmovsldup zmm2, zmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vmovsldup zmm26, zmmword ptr [r8+00000000h]')
diff --git a/tests/0f13.py b/tests/0f13.py
@@ -51,7 +51,7 @@ def test(self):
         myDisasm.read()
         assert_equal(myDisasm.infos.Instruction.Opcode, 0x13)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovlps ')
-        assert_equal(myDisasm.infos.repr, 'vmovlps qword ptr [rax+00000000h], xmm2')
+        assert_equal(myDisasm.infos.repr, 'vmovlps qword ptr [r8+00000000h], xmm26')
 
         # 66 0F 13/r
         # MOVLPD m64, xmm1
@@ -83,4 +83,4 @@ def test(self):
         myDisasm.read()
         assert_equal(myDisasm.infos.Instruction.Opcode, 0x13)
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vmovlpd ')
-        assert_equal(myDisasm.infos.repr, 'vmovlpd qword ptr [rax+00000000h], xmm2')
+        assert_equal(myDisasm.infos.repr, 'vmovlpd qword ptr [r8+00000000h], xmm26')
diff --git a/tests/0f14.py b/tests/0f14.py
@@ -63,7 +63,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x14')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vunpcklps ')
-        assert_equal(myDisasm.infos.repr, 'vunpcklps xmm2, xmm15, xmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vunpcklps xmm26, xmm31, xmmword ptr [r8+00000000h]')
 
         # EVEX.NDS.256.0F.W0 14 /r
         # VUNPCKLPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst
@@ -74,7 +74,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x14')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vunpcklps ')
-        assert_equal(myDisasm.infos.repr, 'vunpcklps ymm2, ymm15, ymmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vunpcklps ymm26, ymm31, ymmword ptr [r8+00000000h]')
 
         # EVEX.NDS.512.0F.W0 14 /r
         # VUNPCKLPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst
@@ -85,7 +85,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x14')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vunpcklps ')
-        assert_equal(myDisasm.infos.repr, 'vunpcklps zmm2, zmm15, zmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vunpcklps zmm26, zmm31, zmmword ptr [r8+00000000h]')
 
         # 66 0F 14 /r
         # UNPCKLPD xmm1, xmm2/m128
@@ -128,7 +128,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x14')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vunpcklpd ')
-        assert_equal(myDisasm.infos.repr, 'vunpcklpd xmm2, xmm15, xmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vunpcklpd xmm26, xmm31, xmmword ptr [r8+00000000h]')
 
         # EVEX.NDS.256.66.0F.W1 14 /r
         # VUNPCKLPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst
@@ -139,7 +139,7 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x14')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vunpcklpd ')
-        assert_equal(myDisasm.infos.repr, 'vunpcklpd ymm2, ymm15, ymmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vunpcklpd ymm26, ymm31, ymmword ptr [r8+00000000h]')
 
         # EVEX.NDS.512.66.0F.W1 14 /r
         # VUNPCKLPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst
@@ -150,4 +150,4 @@ def test(self):
         myDisasm.read()
         assert_equal(hex(myDisasm.infos.Instruction.Opcode), '0x14')
         assert_equal(myDisasm.infos.Instruction.Mnemonic, 'vunpcklpd ')
-        assert_equal(myDisasm.infos.repr, 'vunpcklpd zmm2, zmm15, zmmword ptr [rax+00000000h]')
+        assert_equal(myDisasm.infos.repr, 'vunpcklpd zmm26, zmm31, zmmword ptr [r8+00000000h]')