Fix illegal signal names generated from real literals #757
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
If a real literal was small enough to use E notation with a negative exponent, that negative sign would appear in signal names derived from that expression, which is illegal for both Verilog and Bluesim. We were eliminating decimal points from numbers, but failing to remove negative signs. Instead of removing them, however, we now replace them (with "d" and "neg") so that the value in the name is not misinterpreted.
quark17
force-pushed
the
signal-name-from-real
branch
from
9b8178f to
9370cbc
Compare
This was accidentally missing from the new jobs for testing GHC versions
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
For signals without source names, BSC constructs a name based on the assigned expression. If the expression contains a number, that number appears in the name. BSC filters out a few characters, such as decimal points (
.) but was not eliminating negative signs (-) which can show up if aRealliteral is small enough that E notation with a negative exponent is used. In that case, BSC was generating a signal name with a negative sign in it, which is not legal for names in Verilog or Bluesim. In the Verilog backend, such names are probably inlined anyway, but I ran into a situation ($displayof aRealvalue) where the signal survived in Bluesim and caused a C++ compilation failure.Filtering out the decimal point causes a real number to look like a large integer, which was confusing when I saw such signal names. So instead of fixing this bug by adding
-to the list of characters to be removed, I changed BSC so that it replaced decimal points bydand negative signs byneg, so that the value in the name is not misinterpreted.