This is a hardware synthesizable digital design for the Simplified DES algorithm with a simple single-case testbench code written in Verilog. Following are block diagrams for each building block in S-DES Algorithm.
SDES System Block Diagram
Sub-keys Generation Block Diagram
2-Round Feistel Function Block Diagram
Substitution Boxes
Permutate-10:
3 | 5 | 2 | 7 | 4 | 10 | 1 | 9 | 8 | 6
Permutate-8:
6 | 3 | 7 | 4 | 8 | 5 | 10 | 9
Permutate-4:
2 | 4 | 3 | 1
Expand and Permutate:
4 | 1 | 2 | 3 | 2 | 3 | 4 | 1
Initial Permutation:
2 | 6 | 3 | 1 | 4 | 8 | 5 | 7
Final Permutation (Inverse Initial Permutation / IP^-1):
4 | 1 | 3 | 5 | 7 | 2 | 8 | 6
LS-1: Left Rotation by 1-bit
LS-2: Left Rotation by 2-bit
SW: 4-bit Swap