This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
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Sep 23, 2020 - C
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tl-verilog
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Designed a 32-Bit RISC-V ISA based 5-Stage pipelined CPU in 5 days!! The design involved TL-Verilog coding for a simple pipelined calculator and addressed all the hazards.
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Nov 1, 2020 - C
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