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64-bit enhancments for RC registers
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A new register type called RC64 is introduced, which allows access to
two consecutive 32-bit registers in the case of 64-bit byte and octet
statistics registers.

At the same time, the accumulator for both types of RC registers is
promoted from a Lua number to a uint64_t cdata object.  In addition to
allow maintaining high-capacity counters based on 32-bit registers
(e.g. packet counters), this also avoids conversions from integers to
doubles.
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alexandergall committed May 13, 2015
1 parent 9f7444c commit c52ad03
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Showing 2 changed files with 16 additions and 4 deletions.
3 changes: 3 additions & 0 deletions src/core/lib.lua
Original file line number Diff line number Diff line change
Expand Up @@ -238,6 +238,9 @@ function hexundump(h, n)
end

function comma_value(n) -- credit http://richard.warburton.it
if type(n) == 'cdata' then
n = tonumber(n)
end
if n ~= n then return "NaN" end
local left,num,right = string.match(n,'^([^%d]*%d)(%d*)(.-)$')
return left..(num:reverse():gsub('(%d%d%d)','%1,'):reverse())..right
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17 changes: 13 additions & 4 deletions src/lib/hardware/register.lua
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@

module(...,package.seeall)

local ffi = require("ffi")
local lib = require("core.lib")

--- ### Register object
Expand All @@ -22,9 +23,8 @@ end
function Register:readrc ()
-- XXX JIT of this function is causing register value to be misread.
jit.off(true,true)
local value = self.ptr[0]
self.acc = (self.acc or 0) + value
return self.acc
self.acc[0] = self.acc[0] + self.ptr[0]
return self.acc[0]
end

--- Write a register
Expand All @@ -46,7 +46,7 @@ function Register:wait (bitmask, value)
end

--- For type `RC`: Reset the accumulator to 0.
function Register:reset () self.acc = 0 end
function Register:reset () self.acc[0] = 0ULL end

--- For other registers provide a noop
function Register:noop () end
Expand Down Expand Up @@ -87,6 +87,9 @@ local mt = {
RC = {__index = { read=Register.readrc, reset=Register.reset,
print=Register.printrc},
__call = Register.readrc, __tostring = Register.__tostring},
RC64 = {__index = { read=Register.readrc, reset=Register.reset,
print=Register.printrc},
__call = Register.readrc, __tostring = Register.__tostring},
}

--- Create a register `offset` bytes from `base_ptr`.
Expand All @@ -98,6 +101,12 @@ function new (name, longname, offset, base_ptr, mode)
ptr=base_ptr + offset/4 }
local mt = mt[mode]
assert(mt)
if mode == 'RC' or mode == 'RC64' then
o.acc = ffi.new("uint64_t[1]")
if mode == 'RC64' then
o.ptr = ffi.cast("uint64_t*", o.ptr)
end
end
return setmetatable(o, mt)
end

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