[gba] memory: The most-significant nibble of an address is not 'dont …

…care'.
nba-emu · Oct 8, 2019 · 8a99ab4 · 8a99ab4
1 parent 14785a7
commit 8a99ab4
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Showing 3 changed files with 15 additions and 9 deletions.
diff --git a/src/gba/system/cpu-memory.inl b/src/gba/system/cpu-memory.inl
@@ -46,7 +46,7 @@ inline std::uint32_t CPU::ReadBIOS(std::uint32_t address) {
 }
 
 inline std::uint8_t CPU::ReadByte(std::uint32_t address, ARM::AccessType type) {
-  int page = (address >> 24) & 15;
+  int page = address >> 24;
   int cycles = cycles16[type][page];
 
   if (mmio.waitcnt.prefetch) {
@@ -104,7 +104,7 @@ inline std::uint8_t CPU::ReadByte(std::uint32_t address, ARM::AccessType type) {
 }
 
 inline std::uint16_t CPU::ReadHalf(std::uint32_t address, ARM::AccessType type) {
-  int page = (address >> 24) & 15;
+  int page = address >> 24;
   int cycles = cycles16[type][page];
 
   if (mmio.waitcnt.prefetch) {
@@ -168,7 +168,7 @@ inline std::uint16_t CPU::ReadHalf(std::uint32_t address, ARM::AccessType type)
 }
 
 inline std::uint32_t CPU::ReadWord(std::uint32_t address, ARM::AccessType type) {
-  int page = (address >> 24) & 15;
+  int page = address >> 24;
   int cycles = cycles32[type][page];
 
   if (mmio.waitcnt.prefetch) {
@@ -226,7 +226,7 @@ inline std::uint32_t CPU::ReadWord(std::uint32_t address, ARM::AccessType type)
 }
 
 inline void CPU::WriteByte(std::uint32_t address, std::uint8_t value, ARM::AccessType type) {
-  int page = (address >> 24) & 15;
+  int page = address >> 24;
   int cycles = cycles16[type][page];
 
   // if (page == 8 && (address & 0x1FFFF) == 0)
@@ -266,7 +266,7 @@ inline void CPU::WriteByte(std::uint32_t address, std::uint8_t value, ARM::Acces
 }
 
 inline void CPU::WriteHalf(std::uint32_t address, std::uint16_t value, ARM::AccessType type) {
-  int page = (address >> 24) & 15;
+  int page = address >> 24;
   int cycles = cycles16[type][page];
 
   // if (page == 8 && (address & 0x1FFFF) == 0)
@@ -340,7 +340,7 @@ inline void CPU::WriteHalf(std::uint32_t address, std::uint16_t value, ARM::Acce
 }
 
 inline void CPU::WriteWord(std::uint32_t address, std::uint32_t value, ARM::AccessType type) {
-  int page = (address >> 24) & 15;
+  int page = address >> 24;
   int cycles = cycles32[type][page];
 
   // if (page == 8 && (address & 0x1FFFF) == 0)

diff --git a/src/gba/system/cpu.cpp b/src/gba/system/cpu.cpp
@@ -74,6 +74,12 @@ void CPU::Reset() {
   mmio.waitcnt.phi = 0;
   mmio.waitcnt.prefetch = 0;
   mmio.waitcnt.cgb = 0;
+  for (int i = 16; i < 256; i++) {
+    cycles16[ARM::ACCESS_NSEQ][i] = 1;
+    cycles16[ARM::ACCESS_SEQ ][i] = 1;
+    cycles32[ARM::ACCESS_NSEQ][i] = 1;
+    cycles32[ARM::ACCESS_SEQ ][i] = 1;
+  }
   UpdateCycleLUT();
 
   prefetch.active = false;
@@ -148,7 +154,7 @@ void CPU::PrefetchStep(std::uint32_t address, int cycles) {
 
     prefetch.active = true;
     prefetch.address[prefetch.count] = next_address;
-    prefetch.countdown = (thumb ? cycles16 : cycles32)[ARM::ACCESS_SEQ][(next_address >> 24) & 15];
+    prefetch.countdown = (thumb ? cycles16 : cycles32)[ARM::ACCESS_SEQ][next_address >> 24];
   }
 
   if (IS_ROM_REGION(address)) {

diff --git a/src/gba/system/cpu.hpp b/src/gba/system/cpu.hpp
@@ -147,12 +147,12 @@ class CPU : private ARM::Interface {
   cycle_t ticks_cpu_left = 0;
   cycle_t ticks_to_event = 0;
 
-  int cycles16[2][16] {
+  int cycles16[2][256] {
     { 1, 1, 3, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1 },
     { 1, 1, 3, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1 },
   };
 
-  int cycles32[2][16] {
+  int cycles32[2][256] {
     { 1, 1, 6, 1, 1, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 1 },
     { 1, 1, 6, 1, 1, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 1 }
   };