Zynq-xc7z100-2-ffg1156.txt

Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.17 secs
 
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Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.17 secs
 
--> Reading design: aes_dec.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "aes_dec.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "aes_dec"
Output Format                      : NGC
Target Device                      : xc7z100-2-ffg1156

---- Source Options
Top Module Name                    : aes_dec
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\gfmult_by2.vhd" into library work
Parsing entity <gfmult_by2>.
Parsing architecture <behavioral> of entity <gfmult_by2>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\sbox.vhd" into library work
Parsing entity <sbox>.
Parsing architecture <behavioral> of entity <sbox>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\column_calculator.vhd" into library work
Parsing entity <column_calculator>.
Parsing architecture <rtl> of entity <column_calculator>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\reg.vhd" into library work
Parsing entity <reg>.
Parsing architecture <behavioral> of entity <reg>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\inv_sbox.vhd" into library work
Parsing entity <inv_sbox>.
Parsing architecture <behavioral> of entity <inv_sbox>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\inv_key_sch_round_function.vhd" into library work
Parsing entity <inv_ksch_round_func>.
Parsing architecture <behavioral> of entity <inv_ksch_round_func>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\inv_column_calculator.vhd" into library work
Parsing entity <inv_column_calculator>.
Parsing architecture <rtl> of entity <inv_column_calculator>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\key_schedule.vhd" into library work
Parsing entity <key_schedule>.
Parsing architecture <behavioral> of entity <key_schedule>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\inv_sub_byte.vhd" into library work
Parsing entity <inv_sub_byte>.
Parsing architecture <behavioral> of entity <inv_sub_byte>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\inv_shift_rwos.vhd" into library work
Parsing entity <inv_shift_rows>.
Parsing architecture <rtl> of entity <inv_shift_rows>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\inv_mix_columns.vhd" into library work
Parsing entity <inv_mix_columns>.
Parsing architecture <rtl> of entity <inv_mix_columns>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\controller.vhd" into library work
Parsing entity <controller>.
Parsing architecture <behavioral> of entity <controller>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\add_round_key.vhd" into library work
Parsing entity <add_round_key>.
Parsing architecture <rtl> of entity <add_round_key>.
Parsing VHDL file "\AES-VHDL\AES-DEC\RTL\aes_dec.vhd" into library work
Parsing entity <aes_dec>.
Parsing architecture <rtl> of entity <aes_dec>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <aes_dec> (architecture <rtl>) from library <work>.

Elaborating entity <reg> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <add_round_key> (architecture <rtl>) from library <work>.

Elaborating entity <inv_mix_columns> (architecture <rtl>) from library <work>.

Elaborating entity <inv_column_calculator> (architecture <rtl>) from library <work>.

Elaborating entity <gfmult_by2> (architecture <behavioral>) from library <work>.

Elaborating entity <column_calculator> (architecture <rtl>) from library <work>.

Elaborating entity <inv_shift_rows> (architecture <rtl>) from library <work>.

Elaborating entity <inv_sub_byte> (architecture <behavioral>) from library <work>.

Elaborating entity <inv_sbox> (architecture <behavioral>) from library <work>.
INFO:HDLCompiler:679 - "\AES-VHDL\AES-DEC\RTL\inv_sbox.vhd" Line 289. Case statement is complete. others clause is never selected

Elaborating entity <key_schedule> (architecture <behavioral>) from library <work>.

Elaborating entity <inv_ksch_round_func> (architecture <behavioral>) from library <work>.

Elaborating entity <sbox> (architecture <behavioral>) from library <work>.
INFO:HDLCompiler:679 - "\AES-VHDL\AES-DEC\RTL\sbox.vhd" Line 289. Case statement is complete. others clause is never selected

Elaborating entity <controller> (architecture <behavioral>) from library <work>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <aes_dec>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\aes_dec.vhd".
    Summary:
	inferred   2 Multiplexer(s).
Unit <aes_dec> synthesized.

Synthesizing Unit <reg>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\reg.vhd".
        size = 128
    Found 128-bit register for signal <current_stata>.
    Summary:
	inferred 128 D-type flip-flop(s).
Unit <reg> synthesized.

Synthesizing Unit <add_round_key>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\add_round_key.vhd".
    Summary:
Unit <add_round_key> synthesized.

Synthesizing Unit <inv_mix_columns>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\inv_mix_columns.vhd".
    Summary:
	no macro.
Unit <inv_mix_columns> synthesized.

Synthesizing Unit <inv_column_calculator>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\inv_column_calculator.vhd".
    Summary:
Unit <inv_column_calculator> synthesized.

Synthesizing Unit <gfmult_by2>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\gfmult_by2.vhd".
    Summary:
Unit <gfmult_by2> synthesized.

Synthesizing Unit <column_calculator>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\column_calculator.vhd".
    Summary:
Unit <column_calculator> synthesized.

Synthesizing Unit <inv_shift_rows>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\inv_shift_rwos.vhd".
    Summary:
	no macro.
Unit <inv_shift_rows> synthesized.

Synthesizing Unit <inv_sub_byte>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\inv_sub_byte.vhd".
    Summary:
	no macro.
Unit <inv_sub_byte> synthesized.

Synthesizing Unit <inv_sbox>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\inv_sbox.vhd".
    Found 256x8-bit Read Only RAM for signal <output_byte>
    Summary:
	inferred   1 RAM(s).
Unit <inv_sbox> synthesized.

Synthesizing Unit <key_schedule>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\key_schedule.vhd".
    Summary:
	inferred   1 Multiplexer(s).
Unit <key_schedule> synthesized.

Synthesizing Unit <inv_ksch_round_func>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\inv_key_sch_round_function.vhd".
    Summary:
Unit <inv_ksch_round_func> synthesized.

Synthesizing Unit <sbox>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\sbox.vhd".
    Found 256x8-bit Read Only RAM for signal <output_byte>
    Summary:
	inferred   1 RAM(s).
Unit <sbox> synthesized.

Synthesizing Unit <controller>.
    Related source file is "\AES-VHDL\AES-DEC\RTL\controller.vhd".
    Found 4-bit register for signal <counter.i>.
    Found 5-bit adder for signal <n0036[4:0]> created at line 45.
    Found 8-bit subtractor for signal <GND_17_o_GND_17_o_sub_5_OUT<7:0>> created at line 45.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred   4 D-type flip-flop(s).
Unit <controller> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 20
 256x8-bit single-port Read Only RAM                   : 20
# Adders/Subtractors                                   : 2
 5-bit adder                                           : 1
 8-bit subtractor                                      : 1
# Registers                                            : 3
 128-bit register                                      : 2
 4-bit register                                        : 1
# Multiplexers                                         : 3
 128-bit 2-to-1 multiplexer                            : 3
# Xors                                                 : 107
 128-bit xor2                                          : 1
 24-bit xor2                                           : 1
 32-bit xor2                                           : 3
 8-bit xor2                                            : 86
 8-bit xor3                                            : 16

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <inv_sbox>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_output_byte> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 8-bit                    |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <input_byte>    |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <output_byte>   |          |
    -----------------------------------------------------------------------
Unit <inv_sbox> synthesized (advanced).

Synthesizing (advanced) Unit <sbox>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_output_byte> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 8-bit                    |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <input_byte>    |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <output_byte>   |          |
    -----------------------------------------------------------------------
Unit <sbox> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 20
 256x8-bit single-port distributed Read Only RAM       : 20
# Adders/Subtractors                                   : 2
 5-bit adder                                           : 1
 8-bit subtractor                                      : 1
# Registers                                            : 260
 Flip-Flops                                            : 260
# Multiplexers                                         : 3
 128-bit 2-to-1 multiplexer                            : 3
# Xors                                                 : 107
 128-bit xor2                                          : 1
 24-bit xor2                                           : 1
 32-bit xor2                                           : 3
 8-bit xor2                                            : 86
 8-bit xor3                                            : 16

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <reg> ...

Optimizing unit <aes_dec> ...

Optimizing unit <inv_ksch_round_func> ...

Optimizing unit <controller> ...

Optimizing unit <inv_column_calculator> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block aes_dec, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 260
 Flip-Flops                                            : 260

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : aes_dec.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 1970
#      INV                         : 2
#      LUT2                        : 163
#      LUT3                        : 135
#      LUT4                        : 142
#      LUT5                        : 8
#      LUT6                        : 1040
#      MUXF7                       : 320
#      MUXF8                       : 160
# FlipFlops/Latches                : 260
#      FD                          : 256
#      FDR                         : 4
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 386
#      IBUF                        : 257
#      OBUF                        : 129

Device utilization summary:
---------------------------

Selected Device : 7z100ffg1156-2 


Slice Logic Utilization: 
 Number of Slice Registers:             260  out of  554800     0%  
 Number of Slice LUTs:                 1490  out of  277400     0%  
    Number used as Logic:              1490  out of  277400     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:   1490
   Number with an unused Flip Flop:    1230  out of   1490    82%  
   Number with an unused LUT:             0  out of   1490     0%  
   Number of fully used LUT-FF pairs:   260  out of   1490    17%  
   Number of unique control sets:         2

IO Utilization: 
 Number of IOs:                         387
 Number of bonded IOBs:                 387  out of    400    96%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 260   |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -2

   Minimum period: 3.324ns (Maximum Frequency: 300.806MHz)
   Minimum input arrival time before clock: 1.185ns
   Maximum output required time after clock: 1.243ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 3.324ns (frequency: 300.806MHz)
  Total number of paths / destination ports: 130120 / 260
-------------------------------------------------------------------------
Delay:               3.324ns (Levels of Logic = 7)
  Source:            reg_inst/current_stata_26 (FF)
  Destination:       reg_inst/current_stata_127 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: reg_inst/current_stata_26 to reg_inst/current_stata_127
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               3   0.236   0.417  reg_inst/current_stata_26 (reg_inst/current_stata_26)
     LUT2:I0->O            8   0.043   0.652  plaintext<26>1 (plaintext_26_OBUF)
     LUT6:I0->O            1   0.043   0.405  invsr_input<27>2 (invsr_input<27>2)
     LUT6:I4->O           32   0.043   0.743  invsr_input<27>6 (invsr_input<27>)
     LUT6:I0->O            1   0.043   0.000  inv_sub_byte_inst_gen[15].sbox_inst/Mram_output_byte142 (inv_sub_byte_inst_gen[15].sbox_inst/Mram_output_byte142)
     MUXF7:I1->O           1   0.178   0.000  inv_sub_byte_inst_gen[15].sbox_inst/Mram_output_byte14_f7_0 (inv_sub_byte_inst_gen[15].sbox_inst/Mram_output_byte14_f71)
     MUXF8:I0->O           1   0.128   0.350  inv_sub_byte_inst_gen[15].sbox_inst/Mram_output_byte14_f8 (feedback<127>)
     LUT3:I2->O            1   0.043   0.000  Mmux_mux_output311 (mux_output<127>)
     FD:D                     -0.000          reg_inst/current_stata_127
    ----------------------------------------
    Total                      3.324ns (0.757ns logic, 2.567ns route)
                                       (22.8% logic, 77.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 516 / 260
-------------------------------------------------------------------------
Offset:              1.185ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       controller_inst/counter.i_3 (FF)
  Destination Clock: clk rising

  Data Path: rst to controller_inst/counter.i_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           257   0.000   0.511  rst_IBUF (rst_IBUF)
     INV:I->O              4   0.054   0.356  controller_inst/rst_inv1_INV_0 (controller_inst/rst_inv)
     FDR:R                     0.264          controller_inst/counter.i_0
    ----------------------------------------
    Total                      1.185ns (0.318ns logic, 0.867ns route)
                                       (26.8% logic, 73.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 259 / 129
-------------------------------------------------------------------------
Offset:              1.243ns (Levels of Logic = 2)
  Source:            controller_inst/counter.i_3 (FF)
  Destination:       done (PAD)
  Source Clock:      clk rising

  Data Path: controller_inst/counter.i_3 to done
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             33   0.236   0.625  controller_inst/counter.i_3 (controller_inst/counter.i_3)
     LUT3:I0->O            1   0.043   0.339  controller_inst/done<7>1 (done_OBUF)
     OBUF:I->O                 0.000          done_OBUF (done)
    ----------------------------------------
    Total                      1.243ns (0.279ns logic, 0.964ns route)
                                       (22.4% logic, 77.6% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    3.324|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 22.24 secs
 
--> 

Total memory usage is 4656632 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)