[FEAT] More accurate CPU detection on RISC-V

[xiaoran007]

Description

The current CPU detection on RISCV actually outputs the microarchitecture (extended instructions) of the CPU, rather than the intuitive CPU model NAME. Most of the RISCV chips (with Linux support) today are SOCs, very similar to ARM chips, maybe using the SOC name as the CPU name is more intuitive way.

Motivation

Adding support for RISCV might be worthwhile.

Additional context

Here is an example. The module is Milkv-duoS, which has a SG2000 (cv181x) SOC (1 RISC-V core). Current output is:

CPU: rv64gvcsu

It seems to be possible to get the series name of the SOC from the device tree (/sys/firmware/devicetree/base/compatible):

cvitek,cv181x

This is similar to most ARM devices.

[CarterLi]

Please try the dev build

[xiaoran007]

Yeah, the dev version looks good🤔