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m2k, axi_dac_interpolate: Add auto rearm feature
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This feature will allow the gating each buffer, cyclic included, by a trigger
condition.

Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
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@AndreiGrozav
AndreiGrozav committed Sep 9, 2024
1 parent 4971995 commit 4c613e2
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Showing 5 changed files with 50 additions and 26 deletions.
33 changes: 20 additions & 13 deletions docs/regmap/adi_regmap_interpolate.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ RO
ENDFIELD

FIELD
[15:8] 0x00000003
[15:8] 0x00000005
VERSION_MINOR
RO
ENDFIELD
Expand Down Expand Up @@ -75,13 +75,13 @@ FIELD
[2:0]
FILTERED_INTERPOLATION
RW
Enables the filtered interpolation:
0: No filtered interpolation
1: Interpolation by 10. Result should be corrected by a 1.531 factor
2: Interpolation by 100. Result should be corrected by a 1.168 factor
3: Interpolation by 1000. Result should be corrected by a 1.783 factor
Enables the filtered interpolation:
0: No filtered interpolation
1: Interpolation by 10. Result should be corrected by a 1.531 factor
2: Interpolation by 100. Result should be corrected by a 1.168 factor
3: Interpolation by 1000. Result should be corrected by a 1.783 factor
6: Interpolation by 10000. Result should be corrected by a 1.360 factor
7: Interpolation by 100000. Result should be corrected by a 1.038 factor
7: Interpolation by 100000. Result should be corrected by a 1.038 factor
default: No filtered interpolation
ENDFIELD

Expand Down Expand Up @@ -115,14 +115,14 @@ FIELD
[2:0]
FILTERED_INTERPOLATION
RW
Enables the filtered interpolation:
Enables the filtered interpolation:

0: No filtered interpolation
1: Interpolation by 10. Result should be corrected by a 1.531 factor
2: Interpolation by 100. Result should be corrected by a 1.168 factor
3: Interpolation by 1000. Result should be corrected by a 1.783 factor
0: No filtered interpolation
1: Interpolation by 10. Result should be corrected by a 1.531 factor
2: Interpolation by 100. Result should be corrected by a 1.168 factor
3: Interpolation by 1000. Result should be corrected by a 1.783 factor
6: Interpolation by 10000. Result should be corrected by a 1.360 factor
7: Interpolation by 100000. Result should be corrected by a 1.038 factor
7: Interpolation by 100000. Result should be corrected by a 1.038 factor
default: No filtered interpolation
ENDFIELD

Expand Down Expand Up @@ -212,6 +212,13 @@ TRIGGER_CONFIG
Trigger configuration
ENDREG

FIELD
[20]
Auto rearm trigger
RW
Rearms the trigger on the last(sample) signal of the DMA(per DAC channel)
ENDFIELD

FIELD
[19]
EN_TRIGGER_LA
Expand Down
12 changes: 10 additions & 2 deletions library/axi_dac_interpolate/axi_dac_interpolate.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -51,6 +51,8 @@ module axi_dac_interpolate #(
input dma_valid_b,
output dma_ready_a,
output dma_ready_b,
input last_a,
input last_b,

input dac_enable_a,
input dac_enable_b,
Expand Down Expand Up @@ -131,7 +133,7 @@ module axi_dac_interpolate #(
wire dac_correction_enable_b;
wire [15:0] dac_correction_coefficient_a;
wire [15:0] dac_correction_coefficient_b;
wire [19:0] trigger_config;
wire [20:0] trigger_config;

wire en_start_trigger;
wire en_stop_trigger;
Expand All @@ -156,6 +158,7 @@ module axi_dac_interpolate #(
wire [ 1:0] raw_transfer_en;
wire [15:0] dac_raw_ch_a_data;
wire [15:0] dac_raw_ch_b_data;
wire rearm_on_last_s;

// signal name changes

Expand All @@ -175,6 +178,7 @@ module axi_dac_interpolate #(
assign en_trigger_pins = trigger_config[17:16];
assign en_trigger_adc = trigger_config[18];
assign en_trigger_la = trigger_config[19];
assign rearm_on_last_s = trigger_config[20];

assign trigger_active = |trigger_config[19:16];
assign trigger = (ext_trigger & en_trigger_pins) |
Expand Down Expand Up @@ -224,6 +228,8 @@ module axi_dac_interpolate #(
.dac_int_data (dac_int_data_a),
.dma_ready (dma_ready_a),
.underflow (underflow_a),
.rearm_on_last (rearm_on_last_s),
.last (last_a),

.filter_mask (filter_mask_a),
.interpolation_ratio (interpolation_ratio_a),
Expand Down Expand Up @@ -252,6 +258,8 @@ module axi_dac_interpolate #(
.dac_valid (dac_valid_b),
.dac_valid_out (dac_valid_out_b),
.underflow (underflow_b),
.rearm_on_last (rearm_on_last_s),
.last (last_b),

.dac_enable (dac_enable_b),
.dac_int_data (dac_int_data_b),
Expand Down
12 changes: 9 additions & 3 deletions library/axi_dac_interpolate/axi_dac_interpolate_filter.v
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Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,9 @@ module axi_dac_interpolate_filter #(
output dac_valid_out,
output underflow,

input rearm_on_last,
input last,

input [ 2:0] filter_mask,
input [31:0] interpolation_ratio,
input [15:0] dac_correction_coefficient,
Expand Down Expand Up @@ -105,7 +108,6 @@ module axi_dac_interpolate_filter #(
wire dac_cic_valid;
wire [109:0] dac_cic_data;

wire dma_valid_ch_sync;
wire dma_valid_ch;
wire flush_dma;

Expand All @@ -114,6 +116,7 @@ module axi_dac_interpolate_filter #(

wire transfer_start;
wire transfer_ready;
wire rearm_channel;

// Once enabled the raw value will be selected until the DMA has valid data.
// This is a workaround for when DAC channels are start/stopped independent
Expand Down Expand Up @@ -197,12 +200,13 @@ module axi_dac_interpolate_filter #(
assign transfer_start = !(en_start_trigger ^ trigger) &
transfer_ready & !dma_transfer_suspend;

assign rearm_channel = last & rearm_on_last;
always @(posedge dac_clk) begin
stop_transfer <= transfer_sm == IDLE ? 1'b0 :
(stop_transfer & !clear_stop_flag) |
dma_transfer_suspend |
(en_stop_trigger & trigger) |
(sync_stop_channels & dma_valid & dma_valid_adjacent);
(sync_stop_channels & (dma_valid ^ dma_valid_adjacent));
end

// transfer state machine
Expand All @@ -224,7 +228,9 @@ module axi_dac_interpolate_filter #(
TRANSFER: begin
clear_stop_flag <= 1'b0;
transfer <= 1'b1;
if (stop_transfer) begin
if (rearm_channel) begin
transfer_sm_next <= WAIT;
end else if (stop_transfer) begin
if (flush_dma_in) begin
transfer_sm_next <= FLUSHING;
end else begin
Expand Down
16 changes: 8 additions & 8 deletions library/axi_dac_interpolate/axi_dac_interpolate_reg.v
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ module axi_dac_interpolate_reg(
output dac_correction_enable_b,
output [15:0] dac_correction_coefficient_a,
output [15:0] dac_correction_coefficient_b,
output [19:0] trigger_config,
output [20:0] trigger_config,
// bus interface

input up_rstn,
Expand All @@ -72,7 +72,7 @@ module axi_dac_interpolate_reg(
// internal registers

reg [31:0] up_version = {16'h0002, /* MAJOR */
8'h04, /* MINOR */
8'h05, /* MINOR */
8'h00}; /* PATCH */
reg [31:0] up_scratch = 32'h0;

Expand All @@ -84,7 +84,7 @@ module axi_dac_interpolate_reg(
reg [ 1:0] up_config = 2'h0;
reg [15:0] up_correction_coefficient_a = 16'h0;
reg [15:0] up_correction_coefficient_b = 16'h0;
reg [19:0] up_trigger_config = 20'h0;
reg [20:0] up_trigger_config = 21'h0;
reg [15:0] up_dac_raw_ch_a_data;
reg [15:0] up_dac_raw_ch_b_data;

Expand Down Expand Up @@ -141,7 +141,7 @@ module axi_dac_interpolate_reg(
up_correction_coefficient_b <= up_wdata[15:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h18)) begin
up_trigger_config <= up_wdata[19:0];
up_trigger_config <= up_wdata[20:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h19)) begin
up_dac_raw_ch_a_data <= up_wdata[15:0];
Expand Down Expand Up @@ -170,7 +170,7 @@ module axi_dac_interpolate_reg(
5'h15: up_rdata <= {30'h0,up_config};
5'h16: up_rdata <= {16'h0,up_correction_coefficient_a};
5'h17: up_rdata <= {16'h0,up_correction_coefficient_b};
5'h18: up_rdata <= {12'h0,up_trigger_config};
5'h18: up_rdata <= {11'h0,up_trigger_config};
5'h19: up_rdata <= {up_dac_raw_ch_b_data, up_dac_raw_ch_a_data};
default: up_rdata <= 0;
endcase
Expand All @@ -181,15 +181,15 @@ module axi_dac_interpolate_reg(
end

up_xfer_cntrl #(
.DATA_WIDTH(162)
.DATA_WIDTH(163)
) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_config[1], // 1
up_config[0], // 1
up_correction_coefficient_b,// 16
up_correction_coefficient_a,// 16
up_trigger_config, // 20
up_trigger_config, // 21
up_flags, // 6
up_dac_raw_ch_a_data, // 16
up_dac_raw_ch_b_data, // 16
Expand All @@ -205,7 +205,7 @@ module axi_dac_interpolate_reg(
dac_correction_enable_a, // 1
dac_correction_coefficient_b, // 16
dac_correction_coefficient_a, // 16
trigger_config, // 20
trigger_config, // 21
flags, // 6
dac_raw_ch_a_data, // 16
dac_raw_ch_b_data, // 16
Expand Down
3 changes: 3 additions & 0 deletions projects/m2k/common/m2k_bd.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -266,6 +266,9 @@ ad_connect axi_dac_interpolate/trigger_la logic_analyzer/trigger_out_adc
ad_connect axi_dac_interpolate/dac_valid_out_a axi_ad9963/dma_valid_i
ad_connect axi_dac_interpolate/dac_valid_out_b axi_ad9963/dma_valid_q

ad_connect axi_dac_interpolate/last_a ad9963_dac_dmac_a/m_axis_last
ad_connect axi_dac_interpolate/last_b ad9963_dac_dmac_b/m_axis_last

ad_connect /axi_ad9963/tx_data txd
ad_connect /axi_ad9963/tx_iq txiq
ad_connect /axi_ad9963/tx_clk tx_clk
Expand Down

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