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                         FPGA gateware for Thunderscope hardware.
                                Powered by Migen & LiteX

This repo aims to provide a LiteX based gateware for Thunderscope hardware.

This repo is for now a WIP.

• Python3, Vivado WebPACK
• Either a Vivado-compatible JTAG cable (native or XVCD), or OpenFPGALoader.

$ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
$ chmod +x litex_setup.py
$ sudo ./litex_setup.py init install

$ ./thunderscope --variant=a200t --driver --build --load

Over JTAGBone (on local machine):

$ litex_server --jtag --jtag-config=openocd_xc7_ft232.cfg

Over PCIeBone (on local or remote machine):

$ sudo litex_server --pcie --pcie-bar=0x:00.0 (--host=192.168.1.X if on remote machine)

$ cd software/kernel
$ make
$ sudo ./init.sh
$ cd ../user
$ make

$ cd test
$ ./i2c_test --scan (--host=192.168.1.X if remotely)
$ ./test_adc.py --channels=1 --mode=ramp --afe-coupling=DC --afe-attenuation=10X --pga-preamp=10 --pga-atten=10 --pga-bw=full --pga-offset=128
$ ./test_glscopeclient.py
$ glscopeclient --debug myscope:enjoy-digital:lan:127.0.0.1

The Trenz A100T and A200T modules include a 256Mb SPI Flash chip, the A50T/A35T builds use a 32Mb SPI Flash. The larger chips' bitstream does not fit into the flash used on the smaller design, therefore we have two Flash partition tables.

A35T/A50T (0x80_0000):

A100T/A200T (0x200_0000):

* Write Protected

Note: The barrier images come from XAPP1247 and will force the watchdog to trip and load the fallback image as soon as possible if either the SYNC word is not detected at the beginning of the Primary Bitstream, or the end of startup is missing from the end of the Primary Bitstream. These barrier images are location-agnostic and the same regardless of platform. They each have an entire sector reserved to prevent them from being erased, but are located as close as possible to the Primary Bitstream within their respective sector.