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tn40.c
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/*******************************************************************************
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include "tn40.h"
#include "tn40_fw.h"
static void bdx_scan_pci(void);
uint bdx_force_no_phy_mode = 0;
module_param_named(no_phy, bdx_force_no_phy_mode, int, 0644);
MODULE_PARM_DESC(bdx_force_no_phy_mode, "no_phy=1 - force no phy mode (CX4)");
__initdata static u32 g_ndevices = 0;
__initdata static u32 g_ndevices_loaded = 0;
__initdata spinlock_t g_lock __initdata;
__initdata DEFINE_SPINLOCK(g_lock);
#define LDEV(_vid,_pid,_subdev,_msi,_ports,_phya,_phyb,_name) \
{_vid,_pid,_subdev,_msi,_ports,PHY_TYPE_##_phya,PHY_TYPE_##_phyb}
static struct bdx_device_descr bdx_dev_tbl[] = {
LDEV(TEHUTI_VID, 0x4010, 0x4010, 1, 1, CX4, NA, "TN4010 Clean SROM"),
LDEV(TEHUTI_VID, 0x4020, 0x3015, 1, 1, CX4, NA,
"TN9030 10GbE CX4 Ethernet Adapter"),
#ifdef PHY_MUSTANG
LDEV(TEHUTI_VID, 0x4020, 0x2040, 1, 1, CX4, NA,
"Mustang-200 10GbE Ethernet Adapter"),
#endif
#ifdef PHY_QT2025
LDEV(TEHUTI_VID, 0x4022, 0x3015, 1, 1, QT2025, NA,
"TN9310 10GbE SFP+ Ethernet Adapter"),
LDEV(TEHUTI_VID, 0x4022, 0x4d00, 1, 1, QT2025, NA,
"D-Link DXE-810S 10GbE SFP+ Ethernet Adapter"),
LDEV(TEHUTI_VID, 0x4022, 0x8709, 1, 1, QT2025, NA,
"ASUS XG-C100F 10GbE SFP+ Ethernet Adapter"),
LDEV(TEHUTI_VID, 0x4022, 0x8103, 1, 1, QT2025, NA,
"Edimax 10 Gigabit Ethernet SFP+ PCI Express Adapter"),
#endif
#ifdef PHY_MV88X3120
LDEV(TEHUTI_VID, 0x4024, 0x3015, 1, 1, MV88X3120, NA,
"TN9210 10GBase-T Ethernet Adapter"),
#endif
#ifdef PHY_MV88X3310
LDEV(TEHUTI_VID, 0x4027, 0x3015, 1, 1, MV88X3310, NA,
"TN9710P 10GBase-T/NBASE-T Ethernet Adapter"),
LDEV(TEHUTI_VID, 0x4027, 0x8104, 1, 1, MV88X3310, NA,
"Edimax 10 Gigabit Ethernet PCI Express Adapter"),
LDEV(TEHUTI_VID, 0x4027, 0x0368, 1, 1, MV88X3310, NA,
"Buffalo LGY-PCIE-MG Ethernet Adapter"),
LDEV(TEHUTI_VID, 0x4027, 0x1546, 1, 1, MV88X3310, NA,
"IOI GE10-PCIE4XG202P 10Gbase-T/NBASE-T Ethernet Adapter"),
LDEV(TEHUTI_VID, 0x4027, 0x1001, 1, 1, MV88X3310, NA,
"LR-Link LREC6860BT 10 Gigabit Ethernet Adapter"),
LDEV(TEHUTI_VID, 0x4027, 0x3310, 1, 1, MV88X3310, NA,
"QNAP PCIe Expansion Card"),
#endif
#ifdef PHY_MV88E2010
LDEV(TEHUTI_VID, 0x4527, 0x3015, 1, 1, MV88E2010, NA,
"TN9710Q 5GBase-T/NBASE-T Ethernet Adapter"),
#endif
#ifdef PHY_TLK10232
LDEV(TEHUTI_VID, 0x4026, 0x3015, 1, 1, TLK10232, NA,
"TN9610 10GbE SFP+ Ethernet Adapter"),
LDEV(TEHUTI_VID, 0x4026, 0x1000, 1, 1, TLK10232, NA,
"LR-Link LREC6860AF 10 Gigabit Ethernet Adapter"),
#endif
#ifdef PHY_AQR105
LDEV(TEHUTI_VID, 0x4025, 0x2900, 1, 1, AQR105, NA,
"D-Link DXE-810T 10GBase-T Ethernet Adapter"),
LDEV(TEHUTI_VID, 0x4025, 0x3015, 1, 1, AQR105, NA,
"TN9510 10GBase-T/NBASE-T Ethernet Adapter"),
LDEV(TEHUTI_VID, 0x4025, 0x8102, 1, 1, AQR105, NA,
"Edimax 10 Gigabit Ethernet PCI Express Adapter"),
LDEV(PROMISE_VID, 0x7203, 0x7203, 1, 1, AQR105, NA,
"Promise SANLink3 T1 10 Gigabit Ethernet Adapter"),
#endif
{ 0 }
};
static struct pci_device_id bdx_pci_tbl[] = {
{ TEHUTI_VID, 0x4010, TEHUTI_VID, 0x4010, 0, 0, 0 },
{ TEHUTI_VID, 0x4020, TEHUTI_VID, 0x3015, 0, 0, 0 },
#ifdef PHY_MUSTANG
{ TEHUTI_VID, 0x4020, 0x180C, 0x2040, 0, 0, 0 },
#endif
#ifdef PHY_QT2025
{ TEHUTI_VID, 0x4022, TEHUTI_VID, 0x3015, 0, 0, 0 },
{ TEHUTI_VID, 0x4022, DLINK_VID, 0x4d00, 0, 0, 0 },
{ TEHUTI_VID, 0x4022, ASUS_VID, 0x8709, 0, 0, 0 },
{ TEHUTI_VID, 0x4022, EDIMAX_VID, 0x8103, 0, 0, 0 },
#endif
#ifdef PHY_MV88X3120
{ TEHUTI_VID, 0x4024, TEHUTI_VID, 0x3015, 0, 0, 0 },
#endif
#ifdef PHY_MV88X3310
{ TEHUTI_VID, 0x4027, TEHUTI_VID, 0x3015, 0, 0, 0 },
{ TEHUTI_VID, 0x4027, EDIMAX_VID, 0x8104, 0, 0, 0 },
{ TEHUTI_VID, 0x4027, BUFFALO_VID, 0x0368, 0, 0, 0 },
{ TEHUTI_VID, 0x4027, 0x1546, 0x4027, 0, 0, 0 },
{ TEHUTI_VID, 0x4027, 0x4C52, 0x1001, 0, 0, 0 },
{ TEHUTI_VID, 0x4027, 0x1BAA, 0x3310, 0, 0, 0 },
#endif
#ifdef PHY_MV88E2010
{ TEHUTI_VID, 0x4527, TEHUTI_VID, 0x3015, 0, 0, 0 },
#endif
#ifdef PHY_TLK10232
{ TEHUTI_VID, 0x4026, TEHUTI_VID, 0x3015, 0, 0, 0 },
{ TEHUTI_VID, 0x4026, 0x4C52, 0x1000, 0, 0, 0 },
#endif
#ifdef PHY_AQR105
{ TEHUTI_VID, 0x4025, DLINK_VID, 0x2900, 0, 0, 0 },
{ TEHUTI_VID, 0x4025, TEHUTI_VID, 0x3015, 0, 0, 0 },
{ TEHUTI_VID, 0x4025, EDIMAX_VID, 0x8102, 0, 0, 0 },
{ PROMISE_VID, 0x7203, PROMISE_VID, 0x7203, 0, 0, 0 },
#endif
{ 0 }
};
MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
/* Definitions needed by ISR or NAPI functions */
static void bdx_rx_alloc_buffers(struct bdx_priv *priv);
static void bdx_tx_cleanup(struct bdx_priv *priv);
static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f,
int budget);
static int bdx_tx_init(struct bdx_priv *priv);
static int bdx_rx_init(struct bdx_priv *priv);
static void bdx_tx_free(struct bdx_priv *priv);
static void bdx_rx_free(struct bdx_priv *priv);
/* Definitions needed by FW loading */
static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
static inline int bdx_rxdb_available(struct rxdb *db);
/* Definitions needed by bdx_probe */
static void bdx_ethtool_ops(struct net_device *netdev);
static int bdx_rx_alloc_pages(struct bdx_priv *priv);
static void bdx_rx_free_pages(struct bdx_priv *priv);
#ifdef _DRIVER_RESUME_
static int bdx_suspend(struct device *dev);
static int bdx_resume(struct device *dev);
#endif
/*#define USE_RSS */
#if defined(USE_RSS)
/* bdx_init_rss - Initialize RSS hash HW function.
*
* @priv - NIC private structure
*/
static int bdx_init_rss(struct bdx_priv *priv)
{
int i;
u32 seed;
/* Disable RSS before starting the configuration */
WRITE_REG(priv, regRSS_CNG, 0);
/*
* Notes:
* - We do not care about the CPU, we just need the hash value, the
* Linux kernel is doing the rest of the work for us. We set the
* CPU table length to 0.
*
* - We use random32() to initialize the Toeplitz secret key. This is
* probably not cryptographically secure way but who cares.
*/
/* UPDATE THE HASH SECRET KEY */
seed = (uint32_t) (0xFFFFFFFF & jiffies);
prandom_seed(seed);
for (i = 0; i < 4 * RSS_HASH_LEN; i += 4) {
u32 rnd = prandom_u32();
WRITE_REG(priv, regRSS_HASH_BASE + 4 * i, rnd);
pr_debug("bdx_init_rss() rnd 0x%x\n", rnd);
}
WRITE_REG(priv, regRSS_CNG,
RSS_ENABLED | RSS_HFT_TOEPLITZ |
RSS_HASH_IPV4 | RSS_HASH_TCP_IPV4 |
RSS_HASH_IPV6 | RSS_HASH_TCP_IPV6);
pr_debug("regRSS_CNG =%x\n", READ_REG(priv, regRSS_CNG));
return 0;
}
#else
#define bdx_init_rss(priv)
#endif
#if defined(TN40_DEBUG)
int g_dbg = 0;
#endif
#if defined(TN40_REGLOG)
int g_regLog = 0;
#endif
#if defined (TN40_MEMLOG)
int g_memLog = 0;
#endif
#if defined(TN40_DEBUG)
void dbg_printFifo(struct fifo *m, char *fName)
{
pr_debug("%s fifo:\n", fName);
pr_debug("WPTR 0x%x = 0x%x RPTR 0x%x = 0x%x\n",
m->reg_WPTR, m->wptr, m->reg_RPTR, m->rptr);
}
void dbg_printRegs(struct bdx_priv *priv, char *msg)
{
pr_debug("* %s * \n", msg);
pr_debug("~~~~~~~~~~~~~\n");
pr_debug("veneto:");
pr_debug("pc = 0x%x li = 0x%x ic = %d\n", READ_REG(priv, 0x2300),
READ_REG(priv, 0x2310), READ_REG(priv, 0x2320));
dbg_printFifo(&priv->txd_fifo0.m, (char *)"TXD");
dbg_printFifo(&priv->rxf_fifo0.m, (char *)"RXF");
dbg_printFifo(&priv->rxd_fifo0.m, (char *)"RXD");
pr_debug("~~~~~~~~~~~~~\n");
}
void dbg_printPBL(struct pbl *pbl)
{
pr_debug("pbl: len %u pa_lo 0x%x pa_hi 0x%x\n", pbl->len, pbl->pa_lo,
pbl->pa_hi);
}
void dbg_printPkt(char *pkt, u16 len)
{
int i;
pr_info("RX: len=%d\n", len);
for (i = 0; i < len; i = i + 16)
pr_err
("%.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x ",
(0xff & pkt[i]), (0xff & pkt[i + 1]), (0xff & pkt[i + 2]),
(0xff & pkt[i + 3]), (0xff & pkt[i + 4]),
(0xff & pkt[i + 5]), (0xff & pkt[i + 6]),
(0xff & pkt[i + 7]), (0xff & pkt[i + 8]),
(0xff & pkt[i + 9]), (0xff & pkt[i + 10]),
(0xff & pkt[i + 11]), (0xff & pkt[i + 12]),
(0xff & pkt[i + 13]), (0xff & pkt[i + 14]),
(0xff & pkt[i + 15]));
pr_info("\n");
}
void dbg_printSkb(struct sk_buff *skb)
{
/*
DBG("SKB: len=%d data_len=%d, truesize=%d head=%p "
"data=%p end=0x%x page=%p page_offset=%d size=%d"
"nr_frags=%d\n",
skb->len, skb->data_len, skb->truesize,
skb->head, skb->data, skb->end,
skb_shinfo(skb)->frags[0].page.p ,
skb_shinfo(skb)->frags[0].page_offset,
skb_shinfo(skb)->frags[0].size,
skb_shinfo(skb)->nr_frags) ;
*/
}
void dbg_printIoctl(void)
{
pr_info
("DBG_ON %d, DBG_OFF %d, DBG_SUSPEND %d, DBG_RESUME %d DBG_PRINT_PAGE_TABLE %d\n",
DBG_START_DBG, DBG_STOP_DBG, DBG_SUSPEND, DBG_RESUME,
DBG_PRINT_PAGE_TABLE);
}
#else
#define dbg_printRegs(priv, msg)
#define dbg_printPBL(pbl)
#define dbg_printFifo(m, fName)
#define dbg_printPkt(pkt)
#define dbg_printIoctl()
#endif
#ifdef TN40_THUNDERBOLT
u32 tbReadReg(struct bdx_priv *priv, u32 reg)
{
u32 rVal;
if (!priv->bDeviceRemoved) {
rVal = readl(priv->pBdxRegs + reg);
if (rVal == 0xFFFFFFFF) {
priv->bDeviceRemoved = 1;
}
} else {
rVal = 0xFFFFFFFF;
}
return rVal;
}
#endif
#ifdef REGLOG
int g_regLog = 0;
u32 bdx_readl(struct bdx_priv *priv, u32 reg)
{
u32 val;
#ifdef TN40_THUNDERBOLT
val = tbReadReg(priv, reg);
#else
val = readl(priv->pBdxRegs + reg);
#endif
if (g_regLog) {
pr_info("regR 0x%x = 0x%x\n", (u32) (((u64) reg) & 0xFFFF),
val);
}
return val;
}
#endif
/*************************************************************************
* MDIO Interface *
*************************************************************************/
/* bdx_mdio_get - read MDIO_CMD_STAT until the device is not busy
* @regs - NIC register space pointer
*
* returns the CMD_STAT value read, or -1 (0xFFFFFFFF) for failure
* (since the busy bit should be off, -1 can never be a valid value for
* mdio_get).
*/
u32 bdx_mdio_get(struct bdx_priv *priv)
{
void __iomem *regs = priv->pBdxRegs;
#define BDX_MAX_MDIO_BUSY_LOOPS 1024
int tries = 0;
while (++tries < BDX_MAX_MDIO_BUSY_LOOPS) {
u32 mdio_cmd_stat = readl(regs + regMDIO_CMD_STAT);
if (GET_MDIO_BUSY(mdio_cmd_stat) == 0) {
return mdio_cmd_stat;
}
}
pr_err("MDIO busy!\n");
return 0xFFFFFFFF;
}
/* bdx_mdio_read - read a 16bit word through the MDIO interface
* @priv
* @device - 5 bit device id
* @port - 5 bit port id
* @addr - 16 bit address
* returns a 16bit value or -1 for failure
*/
int bdx_mdio_read(struct bdx_priv *priv, int device, int port, u16 addr)
{
void __iomem *regs = priv->pBdxRegs;
u32 tmp_reg, i;
/* Wait until MDIO is not busy */
if (bdx_mdio_get(priv) == 0xFFFFFFFF) {
return -1;
}
i = ((device & 0x1F) | ((port & 0x1F) << 5));
writel(i, regs + regMDIO_CMD);
writel((u32) addr, regs + regMDIO_ADDR);
if ((tmp_reg = bdx_mdio_get(priv)) == 0xFFFFFFFF) {
pr_err("MDIO busy after read command\n");
return -1;
}
writel(((1 << 15) | i), regs + regMDIO_CMD);
/* Read CMD_STAT until not busy */
if ((tmp_reg = bdx_mdio_get(priv)) == 0xFFFFFFFF) {
pr_err("MDIO busy after read command\n");
return -1;
}
if (GET_MDIO_RD_ERR(tmp_reg)) {
pr_debug("MDIO error after read command\n");
return -1;
}
tmp_reg = readl(regs + regMDIO_DATA);
return (int)(tmp_reg & 0xFFFF);
}
/* bdx_mdio_write - writes a 16bit word through the MDIO interface
* @priv
* @device - 5 bit device id
* @port - 5 bit port id
* @addr - 16 bit address
* @data - 16 bit value
* returns 0 for success or -1 for failure
*/
int bdx_mdio_write(struct bdx_priv *priv, int device, int port, u16 addr,
u16 data)
{
void __iomem *regs = priv->pBdxRegs;
u32 tmp_reg;
/* Wait until MDIO is not busy */
if (bdx_mdio_get(priv) == 0xFFFFFFFF) {
return -1;
}
writel(((device & 0x1F) | ((port & 0x1F) << 5)), regs + regMDIO_CMD);
writel((u32) addr, regs + regMDIO_ADDR);
if (bdx_mdio_get(priv) == 0xFFFFFFFF) {
return -1;
}
writel((u32) data, regs + regMDIO_DATA);
/* Read CMD_STAT until not busy */
if ((tmp_reg = bdx_mdio_get(priv)) == 0xFFFFFFFF) {
pr_err("MDIO busy after write command\n");
return -1;
}
if (GET_MDIO_RD_ERR(tmp_reg)) {
pr_err("MDIO error after write command\n");
return -1;
}
return 0;
}
void setMDIOSpeed(struct bdx_priv *priv, u32 speed)
{
void __iomem *regs = priv->pBdxRegs;
int mdio_cfg;
mdio_cfg = readl(regs + regMDIO_CMD_STAT);
if (1 == speed) {
mdio_cfg = (0x7d << 7) | 0x08; /* 1MHz */
} else {
mdio_cfg = 0xA08; /* 6MHz */
}
mdio_cfg |= (1 << 6);
writel(mdio_cfg, regs + regMDIO_CMD_STAT);
msleep(100);
}
int bdx_mdio_look_for_phy(struct bdx_priv *priv, int port)
{
int phy_id, i;
int rVal = -1;
i = port;
setMDIOSpeed(priv, MDIO_SPEED_1MHZ);
phy_id = bdx_mdio_read(priv, 1, i, 0x0002); /* PHY_ID_HIGH */
phy_id &= 0xFFFF;
for (i = 0; i < 32; i++) {
msleep(10);
pr_debug("LOOK FOR PHY: port=0x%x\n", i);
phy_id = bdx_mdio_read(priv, 1, i, 0x0002); /* PHY_ID_HIGH */
phy_id &= 0xFFFF;
if (phy_id != 0xFFFF && phy_id != 0) {
rVal = i;
break;
}
}
if (rVal == -1) {
pr_err("PHY not found\n");
}
return rVal;
}
static int __init bdx_mdio_phy_search(struct bdx_priv *priv,
void __iomem * regs, int *port_t,
unsigned short *phy_t)
{
int i, phy_id;
char *s;
if (bdx_force_no_phy_mode) {
pr_err("Forced NO PHY mode\n");
i = 0;
} else {
i = bdx_mdio_look_for_phy(priv, *port_t);
if (i >= 0) { /* PHY found */
*port_t = i;
phy_id = bdx_mdio_read(priv, 1, *port_t, 0x0002); /* PHY_ID_HI */
i = phy_id << 16;
phy_id = bdx_mdio_read(priv, 1, *port_t, 0x0003); /* PHY_ID_LOW */
phy_id &= 0xFFFF;
i |= phy_id;
}
}
switch (i) {
#ifdef PHY_QT2025
case 0x0043A400:
*phy_t = PHY_TYPE_QT2025;
s = "QT2025 10Gbps SFP+";
*phy_t = QT2025_register(priv);
break;
#endif
#ifdef PHY_MV88X3120
case 0x01405896:
s = "MV88X3120 10Gbps 10GBase-T";
*phy_t = MV88X3120_register(priv);
break;
#endif
#if (defined PHY_MV88X3310) || (defined PHY_MV88E2010)
case 0x02b09aa:
case 0x02b09ab:
if (priv->deviceId == 0x4027) {
s = (i ==
0x02b09aa) ? "MV88X3310 (A0) 10Gbps 10GBase-T" :
"MV88X3310 (A1) 10Gbps 10GBase-T";
*phy_t = MV88X3310_register(priv);
} else if (priv->deviceId == 0x4527) {
s = (i ==
0x02b09aa) ? "MV88E2010 (A0) 5Gbps 5GBase-T" :
"MV88E2010 (A1) 5Gbps 5GBase-T";
*phy_t = MV88X3310_register(priv);
} else if (priv->deviceId == 0x4010) {
s = "Dummy CX4";
*phy_t = CX4_register(priv);
} else {
s = "";
pr_err("Unsupported device id/phy id 0x%x/0x%x !\n",
priv->pdev->device, i);
}
break;
#endif
#ifdef PHY_TLK10232
case 0x40005100:
s = "TLK10232 10Gbps SFP+";
*phy_t = TLK10232_register(priv);
break;
#endif
#ifdef PHY_AQR105
case 0x03A1B462: /*AQR105 B0 */
case 0x03A1B463: /*AQR105 B1 */
case 0x03A1B4A3: /*AQR105 B1 */
s = "AQR105 10Gbps 10GBase-T";
*phy_t = AQR105_register(priv);
break;
#endif
default:
*phy_t = PHY_TYPE_CX4;
s = "Native 10Gbps CX4";
*phy_t = CX4_register(priv);
break;
}
priv->isr_mask |= IR_TMR1;
setMDIOSpeed(priv, priv->phy_ops.mdio_speed);
pr_info("PHY detected on port %u ID=%X - %s\n", *port_t, i, s);
return (PHY_TYPE_NA == *phy_t) ? -1 : 0;
}
static int __init bdx_mdio_reset(struct bdx_priv *priv, int port,
unsigned short phy)
{
void __iomem *regs = priv->pBdxRegs;
int port_t = ++port;
unsigned short phy_t = phy;
priv->phy_mdio_port = 0xFF;
if (-1 == bdx_mdio_phy_search(priv, regs, &port_t, &phy_t)) {
return -1;
}
if (phy != phy_t) {
pr_err("PHY type by svid %u found %u\n", phy, phy_t);
phy = phy_t;
}
port = port_t;
priv->phy_mdio_port = port;
priv->phy_type = phy;
return priv->phy_ops.mdio_reset(priv, port, phy);
}
/*************************************************************************
* Print Info *
*************************************************************************/
static void print_hw_id(struct pci_dev *pdev)
{
struct pci_nic *nic = pci_get_drvdata(pdev);
u16 pci_link_status = 0;
u16 pci_ctrl = 0;
pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
pr_info("srom 0x%x HWver %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n",
readl(nic->regs + SROM_VER),
readl(nic->regs + FPGA_VER) & 0xFFFF,
readl(nic->regs + FPGA_SEED),
GET_LINK_STATUS_LANES(pci_link_status),
GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
}
static void print_fw_id(struct pci_nic *nic)
{
pr_info("fw 0x%x\n", readl(nic->regs + FW_VER));
}
static void print_eth_id(struct net_device *ndev)
{
pr_info("%s, Port %c\n", ndev->name, (ndev->if_port == 0) ? 'A' : 'B');
}
/*************************************************************************
* Code *
*************************************************************************/
#define bdx_enable_interrupts(priv) do { WRITE_REG(priv, regIMR, priv->isr_mask); } while (0)
#define bdx_disable_interrupts(priv) do { WRITE_REG(priv, regIMR, 0); } while (0)
/* bdx_fifo_init
* Create TX/RX descriptor fifo for host-NIC communication. 1K extra space is
* allocated at the end of the fifo to simplify processing of descriptors that
* wraps around fifo's end.
*
* @priv - NIC private structure
* @f - Fifo to initialize
* @fsz_type - Fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
* @reg_XXX - Offsets of registers relative to base address
*
* Returns 0 on success, negative value on failure
*
*/
static int
bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
{
u16 memsz = FIFO_SIZE * (1 << fsz_type);
memset(f, 0, sizeof(struct fifo));
/* dma_alloc_coherent gives us 4k-aligned memory */
if (f->va == NULL) {
f->va = dma_alloc_coherent(&priv->pdev->dev,
memsz + FIFO_EXTRA_SPACE, &f->da, GFP_ATOMIC);
if (!f->va) {
pr_err("dma_alloc_coherent failed\n");
return -ENOMEM;
}
}
f->reg_CFG0 = reg_CFG0;
f->reg_CFG1 = reg_CFG1;
f->reg_RPTR = reg_RPTR;
f->reg_WPTR = reg_WPTR;
f->rptr = 0;
f->wptr = 0;
f->memsz = memsz;
f->size_mask = memsz - 1;
WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
WRITE_REG(priv, reg_CFG1, H32_64(f->da));
return 0;
}
/* bdx_fifo_free - Free all resources used by fifo
* @priv - Nic private structure
* @f - Fifo to release
*/
static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
{
if (f->va) {
dma_free_coherent(&priv->pdev->dev,
f->memsz + FIFO_EXTRA_SPACE, f->va, (enum dma_data_direction)f->da);
f->va = NULL;
}
}
int bdx_speed_set(struct bdx_priv *priv, u32 speed)
{
int i;
u32 val;
pr_debug("speed %d\n", speed);
switch (speed) {
case SPEED_10000:
case SPEED_5000:
case SPEED_2500:
case SPEED_1000X:
case SPEED_100X:
pr_debug("link_speed %d\n", speed);
WRITE_REG(priv, 0x1010, 0x217); /*ETHSD.REFCLK_CONF */
WRITE_REG(priv, 0x104c, 0x4c); /*ETHSD.L0_RX_PCNT */
WRITE_REG(priv, 0x1050, 0x4c); /*ETHSD.L1_RX_PCNT */
WRITE_REG(priv, 0x1054, 0x4c); /*ETHSD.L2_RX_PCNT */
WRITE_REG(priv, 0x1058, 0x4c); /*ETHSD.L3_RX_PCNT */
WRITE_REG(priv, 0x102c, 0x434); /*ETHSD.L0_TX_PCNT */
WRITE_REG(priv, 0x1030, 0x434); /*ETHSD.L1_TX_PCNT */
WRITE_REG(priv, 0x1034, 0x434); /*ETHSD.L2_TX_PCNT */
WRITE_REG(priv, 0x1038, 0x434); /*ETHSD.L3_TX_PCNT */
WRITE_REG(priv, 0x6300, 0x0400); /*MAC.PCS_CTRL */
WRITE_REG(priv, 0x1018, 0x00); /*Mike2 */
udelay(5);
WRITE_REG(priv, 0x1018, 0x04); /*Mike2 */
udelay(5);
WRITE_REG(priv, 0x1018, 0x06); /*Mike2 */
udelay(5);
/*MikeFix1 */
/*L0: 0x103c , L1: 0x1040 , L2: 0x1044 , L3: 0x1048 =0x81644 */
WRITE_REG(priv, 0x103c, 0x81644); /*ETHSD.L0_TX_DCNT */
WRITE_REG(priv, 0x1040, 0x81644); /*ETHSD.L1_TX_DCNT */
WRITE_REG(priv, 0x1044, 0x81644); /*ETHSD.L2_TX_DCNT */
WRITE_REG(priv, 0x1048, 0x81644); /*ETHSD.L3_TX_DCNT */
WRITE_REG(priv, 0x1014, 0x043); /*ETHSD.INIT_STAT */
for (i = 1000; i; i--) {
udelay(50);
val = READ_REG(priv, 0x1014); /*ETHSD.INIT_STAT */
if (val & (1 << 9)) {
WRITE_REG(priv, 0x1014, 0x3); /*ETHSD.INIT_STAT */
val = READ_REG(priv, 0x1014); /*ETHSD.INIT_STAT */
break;
}
}
if (0 == i) {
pr_err("MAC init timeout!\n");
}
WRITE_REG(priv, 0x6350, 0x0); /*MAC.PCS_IF_MODE */
WRITE_REG(priv, regCTRLST, 0xC13); /*0x93//0x13 */
WRITE_REG(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT */
for (i = 40; i--;) {
udelay(50);
}
WRITE_REG(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT */
break;
case SPEED_1000:
case SPEED_100:
WRITE_REG(priv, 0x1010, 0x613); /*ETHSD.REFCLK_CONF */
WRITE_REG(priv, 0x104c, 0x4d); /*ETHSD.L0_RX_PCNT */
WRITE_REG(priv, 0x1050, 0x0); /*ETHSD.L1_RX_PCNT */
WRITE_REG(priv, 0x1054, 0x0); /*ETHSD.L2_RX_PCNT */
WRITE_REG(priv, 0x1058, 0x0); /*ETHSD.L3_RX_PCNT */
WRITE_REG(priv, 0x102c, 0x35); /*ETHSD.L0_TX_PCNT */
WRITE_REG(priv, 0x1030, 0x0); /*ETHSD.L1_TX_PCNT */
WRITE_REG(priv, 0x1034, 0x0); /*ETHSD.L2_TX_PCNT */
WRITE_REG(priv, 0x1038, 0x0); /*ETHSD.L3_TX_PCNT */
WRITE_REG(priv, 0x6300, 0x01140); /*MAC.PCS_CTRL */
WRITE_REG(priv, 0x1014, 0x043); /*ETHSD.INIT_STAT */
for (i = 1000; i; i--) {
udelay(50);
val = READ_REG(priv, 0x1014); /*ETHSD.INIT_STAT */
if (val & (1 << 9)) {
WRITE_REG(priv, 0x1014, 0x3); /*ETHSD.INIT_STAT */
val = READ_REG(priv, 0x1014); /*ETHSD.INIT_STAT */
break;
}
}
if (0 == i) {
pr_err("MAC init timeout!\n");
}
WRITE_REG(priv, 0x6350, 0x2b); /*MAC.PCS_IF_MODE 1g */
WRITE_REG(priv, 0x6310, 0x9801); /*MAC.PCS_DEV_AB */
WRITE_REG(priv, 0x6314, 0x1); /*MAC.PCS_PART_AB */
WRITE_REG(priv, 0x6348, 0xc8); /*MAC.PCS_LINK_LO */
WRITE_REG(priv, 0x634c, 0xc8); /*MAC.PCS_LINK_HI */
udelay(50);
WRITE_REG(priv, regCTRLST, 0xC13); /*0x93//0x13 */
WRITE_REG(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT */
for (i = 40; i--;) {
udelay(50);
}
WRITE_REG(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT */
WRITE_REG(priv, 0x6300, 0x1140); /*MAC.PCS_CTRL */
break;
case 0: /* Link down */
WRITE_REG(priv, 0x104c, 0x0); /*ETHSD.L0_RX_PCNT */
WRITE_REG(priv, 0x1050, 0x0); /*ETHSD.L1_RX_PCNT */
WRITE_REG(priv, 0x1054, 0x0); /*ETHSD.L2_RX_PCNT */
WRITE_REG(priv, 0x1058, 0x0); /*ETHSD.L3_RX_PCNT */
WRITE_REG(priv, 0x102c, 0x0); /*ETHSD.L0_TX_PCNT */
WRITE_REG(priv, 0x1030, 0x0); /*ETHSD.L1_TX_PCNT */
WRITE_REG(priv, 0x1034, 0x0); /*ETHSD.L2_TX_PCNT */
WRITE_REG(priv, 0x1038, 0x0); /*ETHSD.L3_TX_PCNT */
WRITE_REG(priv, regCTRLST, 0x800);
WRITE_REG(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT */
for (i = 40; i--;) {
udelay(50);
}
WRITE_REG(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT */
break;
default:
pr_err("%s Link speed was not identified yet (%d)\n",
priv->ndev->name, speed);
speed = 0;
break;
}
return speed;
}
void bdx_speed_changed(struct bdx_priv *priv, u32 speed)
{
pr_debug("speed %d\n", speed);
speed = bdx_speed_set(priv, speed);
pr_debug("link_speed %d speed %d\n", priv->link_speed, speed);
if (priv->link_speed != speed) {
priv->link_speed = speed;
pr_debug("%s Speed changed %d\n", priv->ndev->name,
priv->link_speed);
}
}
/*
* bdx_link_changed - Notify the OS about hw link state.
*
* @bdx_priv - HW adapter structure
*/
static void bdx_link_changed(struct bdx_priv *priv)
{
u32 link = priv->phy_ops.link_changed(priv);;
if (!link) {
if (netif_carrier_ok(priv->ndev)) {
netif_stop_queue(priv->ndev);
netif_carrier_off(priv->ndev);
pr_err("%s Link Down\n", priv->ndev->name);
#ifdef _EEE_
if (priv->phy_ops.reset_eee != NULL) {
priv->phy_ops.reset_eee(priv);
}
#endif
}
} else {
if (!netif_carrier_ok(priv->ndev)) {
netif_wake_queue(priv->ndev);
netif_carrier_on(priv->ndev);
pr_info("%s Link Up %s\n", priv->ndev->name,
(priv->link_speed ==
SPEED_10000) ? "10G" : (priv->link_speed ==
SPEED_5000) ? "5G"
: (priv->link_speed ==
SPEED_2500) ? "2.5G" : (priv->link_speed ==
SPEED_1000)
|| (priv->link_speed ==
SPEED_1000X) ? "1G" : (priv->link_speed ==
SPEED_100)
|| (priv->link_speed ==
SPEED_100X) ? "100M" : " ");
}
}
}
static inline void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
{
if (isr & (IR_LNKCHG0 | IR_LNKCHG1 | IR_TMR0)) {
pr_debug("isr = 0x%x\n", isr);
bdx_link_changed(priv);
}
#if 0
if (isr & IR_RX_FREE_0) {
pr_debug("RX_FREE_0\n");
}
if (isr & IR_PCIE_LINK)
pr_err("%s PCI-E Link Fault\n", priv->ndev->name);
if (isr & IR_PCIE_TOUT)
pr_err("%s PCI-E Time Out\n", priv->ndev->name);
#endif
}
/* bdx_isr - Interrupt Service Routine for Bordeaux NIC
* @irq - Interrupt number
* @ndev - Network device
* @regs - CPU registers
*
* Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
*
* Read the ISR register to know interrupt triggers and process them one by
* one.
*
* Interrupt triggers are:
* RX_DESC - A new packet has arrived and RXD fifo holds its descriptor
* RX_FREE - The number of free Rx buffers in RXF fifo gets low
* TX_FREE - A packet was transmitted and RXF fifo holds its descriptor
*/
static irqreturn_t bdx_isr_napi(int irq, void *dev)
{
struct net_device *ndev = dev;
struct bdx_priv *priv = netdev_priv(ndev);
u32 isr;
isr = READ_REG(priv, regISR_MSK0);
if (unlikely(!isr)) {
bdx_enable_interrupts(priv);
return IRQ_NONE; /* Not our interrupt */
}
if (isr & IR_EXTRA)
bdx_isr_extra(priv, isr);
if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0 | IR_TMR1)) {
if (likely(LUXOR__SCHEDULE_PREP(&priv->napi, ndev))) {
LUXOR__SCHEDULE(&priv->napi, ndev);
return IRQ_HANDLED;
} else {
/*
* NOTE: We get here if an interrupt has slept into
* the small time window between these lines in
* bdx_poll:
* bdx_enable_interrupts(priv);
* return 0;
*
* Currently interrupts are disabled (since we
* read the ISR register) and we have failed to
* register the next poll. So we read the regs to
* trigger the chip and allow further interrupts.
*/
READ_REG(priv, regTXF_WPTR_0);
READ_REG(priv, regRXD_WPTR_0);
}
}
bdx_enable_interrupts(priv);
return IRQ_HANDLED;
}
static int bdx_poll(struct napi_struct *napi, int budget)
{
struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
int work_done;
if (!priv->bDeviceRemoved) {
bdx_tx_cleanup(priv);
work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
if (work_done < budget) {
napi_complete(napi);
bdx_enable_interrupts(priv);
}
} else {
work_done = budget;
}
return work_done;
}
/* bdx_fw_load - Load the firmware to the NIC
* @priv - NIC private structure
*
* The firmware is loaded via TXD fifo, which needs be initialized first.
* The firmware needs to be loaded once per NIC and not per PCI device
* provided by NIC (a NIC can have multiple devices). So all the drivers use
* semaphore register to load the FW only once.
*/
static int __init bdx_fw_load(struct bdx_priv *priv)
{
int master, i;
int rVal = 0;
master = READ_REG(priv, regINIT_SEMAPHORE);
if (!READ_REG(priv, regINIT_STATUS) && master) {
pr_debug("Loading FW...\n");
bdx_tx_push_desc_safe(priv, s_firmLoad, sizeof(s_firmLoad));
mdelay(100);
}
for (i = 0; i < 200; i++) {