z80.def

Z80 Native
OPTION LITTLE
CLASS REG16
BC=0,DE=1,HL=2,SP=3
CLASS REG16A
BC=0,DE=1,HL=2,AF=3
CLASS REG8
B=0,C=1,D=2,E=3,H=4,L=5,(HL)=6,A=7
CLASS COND
NZ=0,Z=1,NC=2,C=3,PE=4,PO=5,P=6,M=7
CLASS JRCOND
NZ=0,Z=1,NC=2,C=3
CLASS RST
00H=0,08H=1,10H=2,18H=3,20H=4,28H=5,30H=6,38H=7
CLASS BITS
0=0,1=1,2=2,3=3,4=4,5=5,6=6,7=7
CLASS INDEX
IX=0,IY=1
*
ADD	\{INDEX},BC
DD|1<5 09
ADD	\{INDEX},DE
DD|1<5 19
LD	\{INDEX},\W
DD|1<5 21 lo(2) hi(2)
INC	\{INDEX}
DD|1<5 23
ADD	IX,IX
DD 29
ADD	IY,IY
FD 29
LD	\{INDEX},(\W)
DD|1<5 2A lo(2) hi(2)
DEC	\{INDEX}
DD|1<5 2B
INC	(\{INDEX}\D)
DD|1<5 34 \2
DEC	(\{INDEX}\D)
DD|1<5 35 \2
LD	(\{INDEX}\D),\{REG8}
DD|1<5 70|3 \2
LD	(\{INDEX}\D),\B
DD|1<5 36 \2 \3
ADD	\{INDEX},SP
DD|1<5 39
LD	\{REG8},(\{INDEX}\D)
DD|2<5 46|1<3 \3
ADD	A,(\{INDEX}\D)
DD|1<5 86 \2
ADC	A,(\{INDEX}\D)
DD|1<5 8E \2
SUB	A,(\{INDEX}\D)
DD|1<5 96 \2
SBC	A,(\{INDEX}\D)
DD|1<5 9E \2
AND	(\{INDEX}\D)
DD|1<5 A6 \2
XOR	(\{INDEX}\D)
DD|1<5 AE \2
OR	(\{INDEX}\D)
DD|1<5 B6 \2
CP	(\{INDEX}\D)
DD|1<5 BE \2
RLC	(\{INDEX}\D)
DD|1<5 CB \2 06
RRC	(\{INDEX}\D)
DD|1<5 CB \2 0E
RL	(\{INDEX}\D)
DD|1<5 CB \2 16
RR	(\{INDEX}\D)
DD|1<5 CB \2 1E
SLA	(\{INDEX}\D)
DD|1<5 CB \2 26
SRA	(\{INDEX}\D)
DD|1<5 CB \2 2E
SRL	(\{INDEX}\D)
DD|1<5 CB \2 3E
BIT	\{BITS},(\{INDEX}\D)
DD|2<5 CB \3 46|1<3
RES	\{BITS},(\{INDEX}\D)
DD|2<5 CB \3 86|1<3
SET	\{BITS},(\{INDEX}\D)
DD|2<5 CB \3 C6|1<3
POP	\{INDEX}
DD|1<5 E1
EX	(SP),\{INDEX}
DD|1<5 E3
PUSH	\{INDEX}
DD|1<5 E5
JP	(\{INDEX})
DD|1<5 E9
LD	SP,\{INDEX}
DD|1<5 F9
NOP
00
ADD	A,\{REG8}
80|1
ADD	A,\B
C6 \1
ADD	HL,\{REG16}
09|1<4
ADC	A,\{REG8}
88|1
ADC	A,\B
CE \1
AND	\{REG8}
A0|1
AND	\B
E6 \1
CALL	\{COND},\W
C4|1<3 lo(2) hi(2)
CALL	\W
CD lo(1) hi(1)
CCF
3F
CP	\{REG8}
B8|1
CP	\B
FE \1
CPL
2F
DAA
27
DEC	\{REG8}
05|1<3
DEC	\{REG16}
0B|1<4
DI
F3
DJNZ	\D
10 \1
EI
FB
EX	AF,AF'
08
EX	(SP),HL
E3
EX	DE,HL
EB
EXX
D9
HALT
76
IN	B,(C)
ED 40
IN	C,(C)
ED 48
IN	D,(C)
ED 50
IN	E,(C)
ED 58
IN	H,(C)
ED 60
IN	L,(C)
ED 68
IN	A,(C)
ED 78
IN	A,(\B)
DB \1
INC	\{REG16}
03|1<4
INC	\{REG8}
04|1<3
JP	(HL)
E9
JP	\{COND},\W
C2|1<3 lo(2) hi(2)
JP	\W
C3 lo(1),hi(1)
JR	\{JRCOND},\D
20|1<3 \2
JR	\D
18 \1
LD	I,A
ED 47
LD	A,I
ED 57
LD	R,A
ED 4F
LD	A,R
ED 5F
LD	A,(BC)
0A
LD	A,(DE)
1A
LD	(BC),A
02
LD	(DE),A
12
LD	SP,HL
F9
LD	\{REG8},\{REG8}
40|1<3|2
LD	\{REG8},\B
06|1<3 \2
LD	(\W),\{INDEX}
DD|1<5 22 lo(2) hi(2)
LD	(\W),HL
22 lo(1) hi(1)
LD	HL,(\W)
2A lo(1) hi(1)
LD	\{REG16},\W
01|1<4 lo(2) hi(2)
LD	(\W),A
32 lo(1) hi(1)
LD	A,(\W)
3A lo(1) hi(1)
OR	\{REG8}
B0|1
OR	\B
F6 \1
OUT	(C),B
ED 41
OUT	(C),C
ED 49
OUT	(C),D
ED 51
OUT	(C),E
ED 59
OUT	(C),H
ED 61
OUT	(C),L
ED 69
OUT	(C),A
ED 79
OUT	(\B),A
D3 \1
POP	\{REG16A}
C1|1<4
PUSH	\{REG16A}
C5|1<4
RET
C9
RET	\{COND}
C0|1<3
RLA
17
RLCA
07
RRA
1F
RRCA
0F
RST	\{RST}
C7|1<3
SCF
37
SBC	\{REG8}
98|1
SBC	A,\B
DE \1
SUB	\{REG8}
90|1
SUB	\B
D6 \1
XOR	\{REG8}
A8|1
XOR	\B
EE \1
RLC	\{REG8}
CB 00|1
RRC	\{REG8}
CB 08|1
RL	\{REG8}
CB 10|1
RR	\{REG8}
CB 18|1
SLA	\{REG8}
CB 20|1
SRA	\{REG8}
CB 28|1
SRL	\{REG8}
CB 38|1
BIT	\{BITS},\{REG8}
CB 40|1<3|2
RES	\{BITS},\{REG8}
CB 80|1<3|2
SET	\{BITS},\{REG8}
CB C0|1<3|2
ADC	HL,BC
ED 4A
ADC	HL,DE
ED 5A
ADC	HL,HL
ED 6A
ADC	HL,SP
ED 7A
CPD
ED A9
CPDR
ED B9
CPI
ED A1
CPIR
ED B1
IM	0
ED 46
IM	1
ED 56
IND
ED AA
INDR
ED BA
INI
ED A2
INIR
ED B2
LD	(\W),BC
ED 43 lo(1) hi(1)
LD	(\W),DE
ED 53 lo(1) hi(1)
LD	(\W),SP
ED 73 lo(1) hi(1)
LD	BC,(\W)
ED 4B lo(1) hi(1)
LD	DE,(\W)
ED 5B lo(1) hi(1)
LD	SP,(\W)
ED 7B lo(1) hi(1)
LDD
ED A8
LDDR
ED B8
LDI
ED A0
LDIR
ED B0
NEG
ED 44
OUTD
ED AB
OTDR
ED BB
OUTI
ED A3
OTIR
ED B3
RETI
ED 4D
RETN
ED 45
RLD
ED 6F
RRD
ED 67
SBC	HL,BC
ED 42
SBC	HL,DE
ED 52
SBC	HL,HL
ED 62
SBC	HL,SP
ED 72
ORG	\W
\O1
END	\W
\S1
DB	\L
\1
DS	\W
\B1
EQU	\W
\E1
PUBLIC
\P
LIB PROC
\R
LIB ENDP
\Q
PUBLIC EQU
\P\E1
EXTERN
\X
*