From d7b4ae981dd3c2e04fa4d6aeb04bf1bc257b0ea3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= <rcardenas.rod@gmail.com>
Date: Mon, 20 Nov 2023 14:14:19 +0100
Subject: [PATCH] update Cargo.toml

---
 riscv-rt/Cargo.toml | 7 ++++---
 riscv/Cargo.toml    | 1 +
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index c65c24e5..a368c68f 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -2,20 +2,21 @@
 name = "riscv-rt"
 version = "0.11.0"
 rust-version = "1.59"
-repository = "/~https://github.com/rust-embedded/riscv-rt"
+repository = "/~https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]
 description = "Minimal runtime / startup for RISC-V CPU's"
+documentation = "https://docs.rs/riscv-rt"
 keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
-edition = "2018"
+edition = "2021"
 
 [features]
 s-mode = []
 single-hart = []
 
 [dependencies]
-riscv = "0.10"
+riscv = {path = "../riscv", version = "0.10"}
 riscv-rt-macros = { path = "macros", version = "0.2.0" }
 
 [dev-dependencies]
diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml
index 9606eac5..821ba0e5 100644
--- a/riscv/Cargo.toml
+++ b/riscv/Cargo.toml
@@ -7,6 +7,7 @@ repository = "/~https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]
 description = "Low level access to RISC-V processors"
+documentation = "https://docs.rs/riscv"
 keywords = ["riscv", "register", "peripheral"]
 license = "ISC"