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<p>Header package containing a collection of 128-bit SIMD operations over 64-bit double-precision floating point elements.
<a href="#details">More...</a></p>
<div class="textblock"><code>#include <<a class="el" href="vec__common__ppc_8h_source.html">pveclib/vec_common_ppc.h</a>></code><br />
<code>#include <<a class="el" href="vec__int128__ppc_8h_source.html">pveclib/vec_int128_ppc.h</a>></code><br />
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<p><a href="vec__f64__ppc_8h_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ab56ccacba6a3b48a7a920c7d5b0fe30e"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#ab56ccacba6a3b48a7a920c7d5b0fe30e">vec_absf64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64x)</td></tr>
<tr class="memdesc:ab56ccacba6a3b48a7a920c7d5b0fe30e"><td class="mdescLeft"> </td><td class="mdescRight">Vector double absolute value. <a href="#ab56ccacba6a3b48a7a920c7d5b0fe30e">More...</a><br /></td></tr>
<tr class="separator:ab56ccacba6a3b48a7a920c7d5b0fe30e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6bdfdf013a97ccd6dc20b1447f81d498"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#a6bdfdf013a97ccd6dc20b1447f81d498">vec_all_isfinitef64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:a6bdfdf013a97ccd6dc20b1447f81d498"><td class="mdescLeft"> </td><td class="mdescRight">Return true if all 2x64-bit vector double values are Finite (Not NaN nor Inf). <a href="#a6bdfdf013a97ccd6dc20b1447f81d498">More...</a><br /></td></tr>
<tr class="separator:a6bdfdf013a97ccd6dc20b1447f81d498"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac8f2bf6308d932b9604dbd8c5f8e90da"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#ac8f2bf6308d932b9604dbd8c5f8e90da">vec_all_isinff64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:ac8f2bf6308d932b9604dbd8c5f8e90da"><td class="mdescLeft"> </td><td class="mdescRight">Return true if all 2x64-bit vector double values are infinity. <a href="#ac8f2bf6308d932b9604dbd8c5f8e90da">More...</a><br /></td></tr>
<tr class="separator:ac8f2bf6308d932b9604dbd8c5f8e90da"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3b54640bbaa0ad0921680fe69a66246b"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#a3b54640bbaa0ad0921680fe69a66246b">vec_all_isnanf64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:a3b54640bbaa0ad0921680fe69a66246b"><td class="mdescLeft"> </td><td class="mdescRight">Return true if all 2x64-bit vector double values are NaN. <a href="#a3b54640bbaa0ad0921680fe69a66246b">More...</a><br /></td></tr>
<tr class="separator:a3b54640bbaa0ad0921680fe69a66246b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab63ac21e968bf199eadd72f94b653905"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#ab63ac21e968bf199eadd72f94b653905">vec_all_isnormalf64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:ab63ac21e968bf199eadd72f94b653905"><td class="mdescLeft"> </td><td class="mdescRight">Return true if all 2x64-bit vector double values are normal (Not NaN, Inf, denormal, or zero). <a href="#ab63ac21e968bf199eadd72f94b653905">More...</a><br /></td></tr>
<tr class="separator:ab63ac21e968bf199eadd72f94b653905"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad0b6b22fcc171729b47878782f823ab4"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#ad0b6b22fcc171729b47878782f823ab4">vec_all_issubnormalf64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:ad0b6b22fcc171729b47878782f823ab4"><td class="mdescLeft"> </td><td class="mdescRight">Return true if all 2x64-bit vector double values are subnormal (denormal). <a href="#ad0b6b22fcc171729b47878782f823ab4">More...</a><br /></td></tr>
<tr class="separator:ad0b6b22fcc171729b47878782f823ab4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a27becc842e7270c96c54a00d4a292d54"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#a27becc842e7270c96c54a00d4a292d54">vec_all_iszerof64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:a27becc842e7270c96c54a00d4a292d54"><td class="mdescLeft"> </td><td class="mdescRight">Return true if all 2x64-bit vector double values are +-0.0. <a href="#a27becc842e7270c96c54a00d4a292d54">More...</a><br /></td></tr>
<tr class="separator:a27becc842e7270c96c54a00d4a292d54"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa5108dc5fc533329fdd794f306a6ec3d"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#aa5108dc5fc533329fdd794f306a6ec3d">vec_any_isfinitef64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:aa5108dc5fc533329fdd794f306a6ec3d"><td class="mdescLeft"> </td><td class="mdescRight">Return true if any of 2x64-bit vector double values are Finite (Not NaN nor Inf). <a href="#aa5108dc5fc533329fdd794f306a6ec3d">More...</a><br /></td></tr>
<tr class="separator:aa5108dc5fc533329fdd794f306a6ec3d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a71abdbd1fd938daa250682ef9bbc5e84"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#a71abdbd1fd938daa250682ef9bbc5e84">vec_any_isinff64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:a71abdbd1fd938daa250682ef9bbc5e84"><td class="mdescLeft"> </td><td class="mdescRight">Return true if any of 2x64-bit vector double values are infinity. <a href="#a71abdbd1fd938daa250682ef9bbc5e84">More...</a><br /></td></tr>
<tr class="separator:a71abdbd1fd938daa250682ef9bbc5e84"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad78d13a9a604d48250a0aecba84ce8f2"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#ad78d13a9a604d48250a0aecba84ce8f2">vec_any_isnanf64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:ad78d13a9a604d48250a0aecba84ce8f2"><td class="mdescLeft"> </td><td class="mdescRight">Return true if any of 2x64-bit vector double values are NaN. <a href="#ad78d13a9a604d48250a0aecba84ce8f2">More...</a><br /></td></tr>
<tr class="separator:ad78d13a9a604d48250a0aecba84ce8f2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9c198001c1db455c8a70478fe7c76c8c"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#a9c198001c1db455c8a70478fe7c76c8c">vec_any_isnormalf64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:a9c198001c1db455c8a70478fe7c76c8c"><td class="mdescLeft"> </td><td class="mdescRight">Return true if any of 2x64-bit vector double values are normal (Not NaN, Inf, denormal, or zero). <a href="#a9c198001c1db455c8a70478fe7c76c8c">More...</a><br /></td></tr>
<tr class="separator:a9c198001c1db455c8a70478fe7c76c8c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a96007b688d4c2c6aed732ec1b04a78de"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#a96007b688d4c2c6aed732ec1b04a78de">vec_any_issubnormalf64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:a96007b688d4c2c6aed732ec1b04a78de"><td class="mdescLeft"> </td><td class="mdescRight">Return true if any of 2x64-bit vector double values is subnormal (denormal). <a href="#a96007b688d4c2c6aed732ec1b04a78de">More...</a><br /></td></tr>
<tr class="separator:a96007b688d4c2c6aed732ec1b04a78de"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a47c593b367639924729e7d8fbb044f0e"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#a47c593b367639924729e7d8fbb044f0e">vec_any_iszerof64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:a47c593b367639924729e7d8fbb044f0e"><td class="mdescLeft"> </td><td class="mdescRight">Return true if any of 2x64-bit vector double values are +-0.0. <a href="#a47c593b367639924729e7d8fbb044f0e">More...</a><br /></td></tr>
<tr class="separator:a47c593b367639924729e7d8fbb044f0e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a59d567f31837de74d7fa722b59e73928"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#a59d567f31837de74d7fa722b59e73928">vec_copysignf64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64x, <a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64y)</td></tr>
<tr class="memdesc:a59d567f31837de74d7fa722b59e73928"><td class="mdescLeft"> </td><td class="mdescRight">Copy the sign bit from vf64y merged with magnitude from vf64x and return the resulting vector double values. <a href="#a59d567f31837de74d7fa722b59e73928">More...</a><br /></td></tr>
<tr class="separator:a59d567f31837de74d7fa722b59e73928"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aae0220385a453649170124948f9085f1"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aee93592cb008b78c17e85d1eaa3419e1">vb64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#aae0220385a453649170124948f9085f1">vec_isfinitef64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:aae0220385a453649170124948f9085f1"><td class="mdescLeft"> </td><td class="mdescRight">Return 2x64-bit vector boolean true values for each double element that is Finite (Not NaN nor Inf). <a href="#aae0220385a453649170124948f9085f1">More...</a><br /></td></tr>
<tr class="separator:aae0220385a453649170124948f9085f1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5508cb768d48ffec6e833076fc10b497"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aee93592cb008b78c17e85d1eaa3419e1">vb64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#a5508cb768d48ffec6e833076fc10b497">vec_isinff64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:a5508cb768d48ffec6e833076fc10b497"><td class="mdescLeft"> </td><td class="mdescRight">Return 2x64-bit vector boolean true values for each double, if infinity. <a href="#a5508cb768d48ffec6e833076fc10b497">More...</a><br /></td></tr>
<tr class="separator:a5508cb768d48ffec6e833076fc10b497"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a131162bc90efca47ad3e5513d73c3350"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aee93592cb008b78c17e85d1eaa3419e1">vb64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#a131162bc90efca47ad3e5513d73c3350">vec_isnanf64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:a131162bc90efca47ad3e5513d73c3350"><td class="mdescLeft"> </td><td class="mdescRight">Return 2x64-bit vector boolean true values, for each double NaN value. <a href="#a131162bc90efca47ad3e5513d73c3350">More...</a><br /></td></tr>
<tr class="separator:a131162bc90efca47ad3e5513d73c3350"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8f764b415ce41cbbc504554f779bcbe6"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aee93592cb008b78c17e85d1eaa3419e1">vb64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#a8f764b415ce41cbbc504554f779bcbe6">vec_isnormalf64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:a8f764b415ce41cbbc504554f779bcbe6"><td class="mdescLeft"> </td><td class="mdescRight">Return 2x64-bit vector boolean true values, for each double value, if normal (Not NaN, Inf, denormal, or zero). <a href="#a8f764b415ce41cbbc504554f779bcbe6">More...</a><br /></td></tr>
<tr class="separator:a8f764b415ce41cbbc504554f779bcbe6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aec48e60f9252ceb1d82ecb76cbce08a8"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aee93592cb008b78c17e85d1eaa3419e1">vb64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#aec48e60f9252ceb1d82ecb76cbce08a8">vec_issubnormalf64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:aec48e60f9252ceb1d82ecb76cbce08a8"><td class="mdescLeft"> </td><td class="mdescRight">Return 2x64-bit vector boolean true values, for each double value that is subnormal (denormal). <a href="#aec48e60f9252ceb1d82ecb76cbce08a8">More...</a><br /></td></tr>
<tr class="separator:aec48e60f9252ceb1d82ecb76cbce08a8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0391d8549f3070e515c0f20ed6bea9ac"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aee93592cb008b78c17e85d1eaa3419e1">vb64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#a0391d8549f3070e515c0f20ed6bea9ac">vec_iszerof64</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vf64)</td></tr>
<tr class="memdesc:a0391d8549f3070e515c0f20ed6bea9ac"><td class="mdescLeft"> </td><td class="mdescRight">Return 2x64-bit vector boolean true values, for each double value that is +-0.0. <a href="#a0391d8549f3070e515c0f20ed6bea9ac">More...</a><br /></td></tr>
<tr class="separator:a0391d8549f3070e515c0f20ed6bea9ac"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aabd670e9d3dd600198336708bb71fe77"><td class="memItemLeft" align="right" valign="top">static long double </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#aabd670e9d3dd600198336708bb71fe77">vec_pack_longdouble</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> lval)</td></tr>
<tr class="memdesc:aabd670e9d3dd600198336708bb71fe77"><td class="mdescLeft"> </td><td class="mdescRight">Copy the pair of doubles from a vector to IBM long double. <a href="#aabd670e9d3dd600198336708bb71fe77">More...</a><br /></td></tr>
<tr class="separator:aabd670e9d3dd600198336708bb71fe77"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac396fe321d73f75b57ebab8c365e20f3"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f64__ppc_8h.html#ac396fe321d73f75b57ebab8c365e20f3">vec_unpack_longdouble</a> (long double lval)</td></tr>
<tr class="memdesc:ac396fe321d73f75b57ebab8c365e20f3"><td class="mdescLeft"> </td><td class="mdescRight">Copy the pair of doubles from a IBM long double to a vector double. <a href="#ac396fe321d73f75b57ebab8c365e20f3">More...</a><br /></td></tr>
<tr class="separator:ac396fe321d73f75b57ebab8c365e20f3"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Header package containing a collection of 128-bit SIMD operations over 64-bit double-precision floating point elements. </p>
<p>Many vector double-precision (64-bit float) operations are implemented with PowerISA-2.06 Vector Scalar Extended (VSX) (POWER7 and later) instructions. Most VSX instructions provide access to 64 combined scalar/vector registers. PowerISA-3.0 (POWER9) provides additional vector double operations: convert with round, convert to/from integer, insert/extract exponent and significand, and test data class. Most of these operations (compiler built-ins, or intrinsics) are defined in <altivec.h> and described in the <a href="https://gcc.gnu.org/onlinedocs/">compiler documentation</a>.</p>
<dl class="section note"><dt>Note</dt><dd>The compiler disables associated <altivec.h> built-ins if the <b>mcpu</b> target does not enable the specific instruction. For example if you compile with <b>-mcpu=power8</b>, the double-precision vector converts, insert/extract and test data class built-ins are are not defined. This header provides the appropriate substitutions, will generate the minimum code, appropriate for the target, and produce correct results.</dd>
<dd>
Most ppc64le compilers will default to -mcpu=power8 if not specified.</dd>
<dd>
GCC 7.3 defines vector forms of the test data class, extract significand, and extract/insert_exp for float and double. These built-ins are not defined in GCC 6.4. See <a href="https://gcc.gnu.org/onlinedocs/">compiler documentation</a>. These are useful operations and can be implemented in a few vector logical instructions for earlier machines.</dd></dl>
<p>So it is reasonable for this header to provide vector forms of the double-precision floating point classification functions (isnormal/subnormal/finite/inf/nan/zero, etc.). These functions can be implemented directly using (one or more) POWER9 instructions, or a few vector logical and integer compare instructions for POWER7/8. Each is comfortably small enough to be in-lined and inherently faster than the equivalent POSIX or compiler built-in runtime scalar functions.</p>
<p>Most of these operations are implemented in a few instructions on newer (POWER7/POWER8/POWER9) processors. This header serves to fill in functional gaps for older (POWER7, POWER8) processors and provides an inline assembler implementation for older compilers that do not provide the built-ins.</p>
<p>This header covers operations that are any of the following:</p>
<ul>
<li>Implemented in hardware instructions in newer processors, but useful to programmers on slightly older processors (even if the equivalent function requires more instructions).</li>
<li>Defined in the OpenPOWER ABI but <em>not</em> yet defined in <altivec.h> provided by available compilers in common use. Examples include vector double even/odd conversions.</li>
<li>Providing special vector double tests for special conditions without generating extraneous floating-point exceptions. This is important for implementing vectorized forms of ISO C99 Math functions. Examples include vector double isnan, isinf, etc.</li>
<li>Commonly used operations, not covered by the ABI or <altivec.h>, and require multiple instructions or are not obvious. For example, converts that change element size and imply converting two vectors into one vector of smaller elements, or one vector into two vectors of larger elements. Another example is the special case of packing/unpacking an IBM long double between a pair of floating-point registers (FPRs) and a single vector register (VR).</li>
</ul>
<h1><a class="anchor" id="f64_examples_0_0"></a>
Examples</h1>
<p>For example: using the the classification functions for implementing the math library function sine and cosine. The POSIX specification requires that special input values are processed without raising extraneous floating point exceptions and return specific floating point values in response. For example, the sin() function.</p><ul>
<li>If the input <em>value</em> is NaN then return a NaN.</li>
<li>If the input <em>value</em> is +-0.0 then return <em>value</em>.</li>
<li>If the input <em>value</em> is subnormal then return <em>value</em>.</li>
<li>If the input <em>value</em> is +-Inf then return a quiet-NaN.</li>
<li>Otherwise compute and return sin(value).</li>
</ul>
<p>The following code example uses functions from this header to address the POSIX requirements for special values input to for a vectorized sinf(): </p><div class="fragment"><div class="line"><a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a></div><div class="line">test_vec_sinf64 (<a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> value)</div><div class="line">{</div><div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vec_f0 = { 0.0, 0.0 };</div><div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> vec_f64_qnan =</div><div class="line"> { 0x7ff8000000000000, 0x7ff8000000000000 };</div><div class="line"> <a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> result;</div><div class="line"> <a class="code" href="vec__common__ppc_8h.html#aee93592cb008b78c17e85d1eaa3419e1">vb64_t</a> normmask, infmask;</div><div class="line"></div><div class="line"> normmask = <a class="code" href="vec__f64__ppc_8h.html#a8f764b415ce41cbbc504554f779bcbe6">vec_isnormalf64</a> (value);</div><div class="line"> <span class="keywordflow">if</span> (<a class="code" href="vec__f64__ppc_8h.html#a9c198001c1db455c8a70478fe7c76c8c">vec_any_isnormalf64</a> (value))</div><div class="line"> {</div><div class="line"> <span class="comment">// replace non-normal input values with safe values.</span></div><div class="line"> <a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> safeval = vec_sel (vec_f0, value, normmask);</div><div class="line"> <span class="comment">// body of vec_sin(safeval) computation elided for this example.</span></div><div class="line"> }</div><div class="line"> <span class="keywordflow">else</span></div><div class="line"> result = value;</div><div class="line"></div><div class="line"> <span class="comment">// merge non-normal input values back into result</span></div><div class="line"> result = vec_sel (value, result, normmask);</div><div class="line"> <span class="comment">// Inf input value elements return quiet-nan.</span></div><div class="line"> infmask = <a class="code" href="vec__f64__ppc_8h.html#a5508cb768d48ffec6e833076fc10b497">vec_isinff64</a> (value);</div><div class="line"> result = vec_sel (result, (<a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a>) vec_f64_qnan, infmask);</div><div class="line"></div><div class="line"> <span class="keywordflow">return</span> result;</div><div class="line">}</div></div><!-- fragment --><p> The code generated for this fragment runs between 24 (-mcpu=power9) and 40 (-mcpu=power8) instructions. The normal execution path is 14 to 25 instructions respectively.</p>
<p>Another example the cos() function.</p><ul>
<li>If the input <em>value</em> is NaN then return a NaN.</li>
<li>If the input <em>value</em> is +-0.0 then return <em>1.0</em>.</li>
<li>If the input <em>value</em> is +-Inf then return a quiet-NaN.</li>
<li>Otherwise compute and return cos(value).</li>
</ul>
<p>The following code example uses functions from this header to address the POSIX requirements for special values input to vectorized cosf(): </p><div class="fragment"><div class="line"><a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a></div><div class="line">test_vec_cosf64 (<a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> value)</div><div class="line">{</div><div class="line"> <a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> result;</div><div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vec_f0 = { 0.0, 0.0 };</div><div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vec_f1 = { 1.0, 1.0 };</div><div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> vec_f64_qnan =</div><div class="line"> { 0x7ff8000000000000, 0x7ff8000000000000 };</div><div class="line"> <a class="code" href="vec__common__ppc_8h.html#aee93592cb008b78c17e85d1eaa3419e1">vb64_t</a> finitemask, infmask, zeromask;</div><div class="line"></div><div class="line"> finitemask = <a class="code" href="vec__f64__ppc_8h.html#aae0220385a453649170124948f9085f1">vec_isfinitef64</a> (value);</div><div class="line"> <span class="keywordflow">if</span> (<a class="code" href="vec__f64__ppc_8h.html#aa5108dc5fc533329fdd794f306a6ec3d">vec_any_isfinitef64</a> (value))</div><div class="line"> {</div><div class="line"> <span class="comment">// replace non-finite input values with safe values.</span></div><div class="line"> <a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> safeval = vec_sel (vec_f0, value, finitemask);</div><div class="line"> <span class="comment">// body of vec_sin(safeval) computation elided for this example.</span></div><div class="line"> }</div><div class="line"> <span class="keywordflow">else</span></div><div class="line"> result = value;</div><div class="line"></div><div class="line"> <span class="comment">// merge non-finite input values back into result</span></div><div class="line"> result = vec_sel (value, result, finitemask);</div><div class="line"> <span class="comment">// Set +-0.0 input elements to exactly 1.0 in result.</span></div><div class="line"> zeromask = <a class="code" href="vec__f64__ppc_8h.html#a0391d8549f3070e515c0f20ed6bea9ac">vec_iszerof64</a> (value);</div><div class="line"> result = vec_sel (result, vec_f1, zeromask);</div><div class="line"> <span class="comment">// Set Inf input elements to quiet-nan in result.</span></div><div class="line"> infmask = <a class="code" href="vec__f64__ppc_8h.html#a5508cb768d48ffec6e833076fc10b497">vec_isinff64</a> (value);</div><div class="line"> result = vec_sel (result, (<a class="code" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a>) vec_f64_qnan, infmask);</div><div class="line"></div><div class="line"> <span class="keywordflow">return</span> result;</div><div class="line">}</div></div><!-- fragment --><p>Neither example raises floating point exceptions or sets <b>errno</b>, as appropriate for a vector math library.</p>
<h1><a class="anchor" id="f64_perf_0_0"></a>
Performance data.</h1>
<p>High level performance estimates are provided as an aid to function selection when evaluating algorithms. For background on how <em>Latency</em> and <em>Throughput</em> are derived see: <a class="el" href="index.html#perf_data">Performance data.</a> </p>
</div><h2 class="groupheader">Function Documentation</h2>
<a id="ab56ccacba6a3b48a7a920c7d5b0fe30e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab56ccacba6a3b48a7a920c7d5b0fe30e">◆ </a></span>vec_absf64()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vec_absf64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64x</em></td><td>)</td>
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<p>Vector double absolute value. </p>
<table class="doxtable">
<tr>
<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
<tr>
<td align="right">power8 </td><td align="center">6-7 </td><td align="left">2/cycle </td></tr>
<tr>
<td align="right">power9 </td><td align="center">2 </td><td align="left">2/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vf64x</td><td>vector double values containing the magnitudes. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>vector double absolute values of vf64x. </dd></dl>
</div>
</div>
<a id="a6bdfdf013a97ccd6dc20b1447f81d498"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6bdfdf013a97ccd6dc20b1447f81d498">◆ </a></span>vec_all_isfinitef64()</h2>
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<td class="memname">static int vec_all_isfinitef64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return true if all 2x64-bit vector double values are Finite (Not NaN nor Inf). </p>
<p>A IEEE Binary64 finite value has an exponent between 0x000 and 0x7fe (a 0x7ff indicates NaN or Inf). The significand can be any value. The sign bit is ignored.</p>
<table class="doxtable">
<tr>
<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
<tr>
<td align="right">power8 </td><td align="center">4-20 </td><td align="left">2/cycle </td></tr>
<tr>
<td align="right">power9 </td><td align="center">6 </td><td align="left">1/cycle </td></tr>
</table>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal __binary64 compare can.</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>an int containing 0 or 1. </dd></dl>
</div>
</div>
<a id="ac8f2bf6308d932b9604dbd8c5f8e90da"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac8f2bf6308d932b9604dbd8c5f8e90da">◆ </a></span>vec_all_isinff64()</h2>
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<td class="memname">static int vec_all_isinff64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return true if all 2x64-bit vector double values are infinity. </p>
<p>A IEEE Binary64 infinity has a exponent of 0x7ff and significand of all zeros. The sign bit is ignored.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
<table class="doxtable">
<tr>
<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
<tr>
<td align="right">power8 </td><td align="center">6-20 </td><td align="left">2/cycle </td></tr>
<tr>
<td align="right">power9 </td><td align="center">6 </td><td align="left">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>boolean int, true if all 2 double values are infinity </dd></dl>
</div>
</div>
<a id="a3b54640bbaa0ad0921680fe69a66246b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3b54640bbaa0ad0921680fe69a66246b">◆ </a></span>vec_all_isnanf64()</h2>
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<td class="memname">static int vec_all_isnanf64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return true if all 2x64-bit vector double values are NaN. </p>
<p>A IEEE Binary64 NaN value has an exponent between 0x7ff and the significand is nonzero. The sign bit is ignored.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
<table class="doxtable">
<tr>
<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
<tr>
<td align="right">power8 </td><td align="center">6-20 </td><td align="left">2/cycle </td></tr>
<tr>
<td align="right">power9 </td><td align="center">6 </td><td align="left">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>a boolean int, true if all 2 vector double values are NaN. </dd></dl>
</div>
</div>
<a id="ab63ac21e968bf199eadd72f94b653905"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab63ac21e968bf199eadd72f94b653905">◆ </a></span>vec_all_isnormalf64()</h2>
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<td class="memname">static int vec_all_isnormalf64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return true if all 2x64-bit vector double values are normal (Not NaN, Inf, denormal, or zero). </p>
<p>A IEEE Binary64 normal value has an exponent between 0x001 and 0x7fe (a 0x7ff indicates NaN or Inf). The significand can be any value (expect 0 if the exponent is zero). The sign bit is ignored.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
<table class="doxtable">
<tr>
<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
<tr>
<td align="right">power8 </td><td align="center">10-28 </td><td align="left">1/cycle </td></tr>
<tr>
<td align="right">power9 </td><td align="center">6 </td><td align="left">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>a boolean int, true if all 2 vector double values are normal. </dd></dl>
</div>
</div>
<a id="ad0b6b22fcc171729b47878782f823ab4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad0b6b22fcc171729b47878782f823ab4">◆ </a></span>vec_all_issubnormalf64()</h2>
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<td class="memname">static int vec_all_issubnormalf64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return true if all 2x64-bit vector double values are subnormal (denormal). </p>
<p>A IEEE Binary64 subnormal has an exponent of 0x000 and a nonzero significand. The sign bit is ignored.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
<table class="doxtable">
<tr>
<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
<tr>
<td align="right">power8 </td><td align="center">10-30 </td><td align="left">1/cycle </td></tr>
<tr>
<td align="right">power9 </td><td align="center">6 </td><td align="left">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>a boolean int, true if all of 2 vector double values are subnormal. </dd></dl>
</div>
</div>
<a id="a27becc842e7270c96c54a00d4a292d54"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a27becc842e7270c96c54a00d4a292d54">◆ </a></span>vec_all_iszerof64()</h2>
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<td class="memname">static int vec_all_iszerof64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return true if all 2x64-bit vector double values are +-0.0. </p>
<p>A IEEE Binary64 zero has an exponent of 0x000 and a zero significand. The sign bit is ignored.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
<table class="doxtable">
<tr>
<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
<tr>
<td align="right">power8 </td><td align="center">6-20 </td><td align="left">2/cycle </td></tr>
<tr>
<td align="right">power9 </td><td align="center">6 </td><td align="left">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>a boolean int, true if all 2 vector double values are +/- zero. </dd></dl>
</div>
</div>
<a id="aa5108dc5fc533329fdd794f306a6ec3d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa5108dc5fc533329fdd794f306a6ec3d">◆ </a></span>vec_any_isfinitef64()</h2>
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<td class="memname">static int vec_any_isfinitef64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return true if any of 2x64-bit vector double values are Finite (Not NaN nor Inf). </p>
<p>A IEEE Binary64 finite value has an exponent between 0x000 and 0x7fe (a 0x7ff indicates NaN or Inf). The significand can be any value. The sign bit is ignored.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
<table class="doxtable">
<tr>
<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
<tr>
<td align="right">power8 </td><td align="center">4-20 </td><td align="left">2/cycle </td></tr>
<tr>
<td align="right">power9 </td><td align="center">6 </td><td align="left">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>an int containing 0 or 1. </dd></dl>
</div>
</div>
<a id="a71abdbd1fd938daa250682ef9bbc5e84"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a71abdbd1fd938daa250682ef9bbc5e84">◆ </a></span>vec_any_isinff64()</h2>
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<td class="memname">static int vec_any_isinff64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return true if any of 2x64-bit vector double values are infinity. </p>
<p>A IEEE Binary64 infinity has a exponent of 0x7ff and significand of all zeros.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
<table class="doxtable">
<tr>
<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
<tr>
<td align="right">power8 </td><td align="center">6-20 </td><td align="left">2/cycle </td></tr>
<tr>
<td align="right">power9 </td><td align="center">6 </td><td align="left">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vf64</td><td>a vector of __binary32 values. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>boolean int, true if any of 2 double values are infinity </dd></dl>
</div>
</div>
<a id="ad78d13a9a604d48250a0aecba84ce8f2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad78d13a9a604d48250a0aecba84ce8f2">◆ </a></span>vec_any_isnanf64()</h2>
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<td class="memname">static int vec_any_isnanf64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return true if any of 2x64-bit vector double values are NaN. </p>
<p>A IEEE Binary64 NaN value has an exponent between 0x7ff and the significand is nonzero. The sign bit is ignored.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
<table class="doxtable">
<tr>
<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
<tr>
<td align="right">power8 </td><td align="center">6-20 </td><td align="left">2/cycle </td></tr>
<tr>
<td align="right">power9 </td><td align="center">6 </td><td align="left">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>a boolean int, true if any of 2 vector double values are NaN. </dd></dl>
</div>
</div>
<a id="a9c198001c1db455c8a70478fe7c76c8c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9c198001c1db455c8a70478fe7c76c8c">◆ </a></span>vec_any_isnormalf64()</h2>
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<td class="memname">static int vec_any_isnormalf64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return true if any of 2x64-bit vector double values are normal (Not NaN, Inf, denormal, or zero). </p>
<p>A IEEE Binary64 normal value has an exponent between 0x001 and 0x7fe (a 0x7ff indicates NaN or Inf). The significand can be any value (expect 0 if the exponent is zero). The sign bit is ignored.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
<table class="doxtable">
<tr>
<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
<tr>
<td align="right">power8 </td><td align="center">6-20 </td><td align="left">1/cycle </td></tr>
<tr>
<td align="right">power9 </td><td align="center">6 </td><td align="left">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>a boolean int, true if any of 2 vector double values are normal. </dd></dl>
</div>
</div>
<a id="a96007b688d4c2c6aed732ec1b04a78de"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a96007b688d4c2c6aed732ec1b04a78de">◆ </a></span>vec_any_issubnormalf64()</h2>
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<td class="memname">static int vec_any_issubnormalf64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return true if any of 2x64-bit vector double values is subnormal (denormal). </p>
<p>A IEEE Binary64 subnormal has an exponent of 0x000 and a nonzero significand. The sign bit is ignored.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
<table class="doxtable">
<tr>
<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
<tr>
<td align="right">power8 </td><td align="center">10-18 </td><td align="left">1/cycle </td></tr>
<tr>
<td align="right">power9 </td><td align="center">6 </td><td align="left">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true if any of 2 vector double values are subnormal. </dd></dl>
</div>
</div>
<a id="a47c593b367639924729e7d8fbb044f0e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a47c593b367639924729e7d8fbb044f0e">◆ </a></span>vec_any_iszerof64()</h2>
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<td class="memname">static int vec_any_iszerof64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
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<p>Return true if any of 2x64-bit vector double values are +-0.0. </p>
<p>A IEEE Binary64 zero has an exponent of 0x000 and a zero significand. The sign bit is ignored.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
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<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
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<td align="right">power8 </td><td align="center">6-20 </td><td align="left">2/cycle </td></tr>
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<td align="right">power9 </td><td align="center">6 </td><td align="left">1/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>a boolean int, true if any of 2 vector double values are +/- zero. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a59d567f31837de74d7fa722b59e73928">◆ </a></span>vec_copysignf64()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> vec_copysignf64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64x</em>, </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64y</em> </td>
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<p>Copy the sign bit from vf64y merged with magnitude from vf64x and return the resulting vector double values. </p>
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<td align="right">power8 </td><td align="center">6-7 </td><td align="left">2/cycle </td></tr>
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<td align="right">power9 </td><td align="center">2 </td><td align="left">2/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramname">vf64x</td><td>vector double values containing the magnitudes. </td></tr>
<tr><td class="paramname">vf64y</td><td>vector double values containing the sign bits. </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>vector double values with magnitude from vf64x and the sign of vf64y. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#aae0220385a453649170124948f9085f1">◆ </a></span>vec_isfinitef64()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aee93592cb008b78c17e85d1eaa3419e1">vb64_t</a> vec_isfinitef64 </td>
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<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return 2x64-bit vector boolean true values for each double element that is Finite (Not NaN nor Inf). </p>
<p>A IEEE Binary64 finite value has an exponent between 0x000 and 0x7fe (a 0x7ff indicates NaN or Inf). The significand can be any value.</p>
<p>Using the vec_cmpeq conditional to generate the predicate mask for NaN / Inf and then invert this for the finite condition. The sign bit is ignored.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
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<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
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<td align="right">power8 </td><td align="center">6-15 </td><td align="left">2/cycle </td></tr>
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<td align="right">power9 </td><td align="center">5 </td><td align="left">2/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
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</dd>
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<dl class="section return"><dt>Returns</dt><dd>a vector boolean long, each containing all 0s(false) or 1s(true). </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a5508cb768d48ffec6e833076fc10b497">◆ </a></span>vec_isinff64()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aee93592cb008b78c17e85d1eaa3419e1">vb64_t</a> vec_isinff64 </td>
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<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return 2x64-bit vector boolean true values for each double, if infinity. </p>
<p>A IEEE Binary64 infinity has a exponent of 0x7ff and significand of all zeros.</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
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<td align="right">power8 </td><td align="center">4-13 </td><td align="left">2/cycle </td></tr>
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<td align="right">power9 </td><td align="center">3 </td><td align="left">2/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>a vector boolean long long, each containing all 0s(false) or 1s(true). </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a131162bc90efca47ad3e5513d73c3350">◆ </a></span>vec_isnanf64()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aee93592cb008b78c17e85d1eaa3419e1">vb64_t</a> vec_isnanf64 </td>
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<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return 2x64-bit vector boolean true values, for each double NaN value. </p>
<p>A IEEE Binary64 NaN value has an exponent between 0x7ff and the significand is nonzero. The sign bit is ignored.</p>
<table class="doxtable">
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<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
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<td align="right">power8 </td><td align="center">4-13 </td><td align="left">2/cycle </td></tr>
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<td align="right">power9 </td><td align="center">3 </td><td align="left">2/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
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</dd>
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<dl class="section return"><dt>Returns</dt><dd>a vector boolean long long, each containing all 0s(false) or 1s(true). </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a8f764b415ce41cbbc504554f779bcbe6">◆ </a></span>vec_isnormalf64()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aee93592cb008b78c17e85d1eaa3419e1">vb64_t</a> vec_isnormalf64 </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td>
<td class="paramname"><em>vf64</em></td><td>)</td>
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<p>Return 2x64-bit vector boolean true values, for each double value, if normal (Not NaN, Inf, denormal, or zero). </p>
<p>A IEEE Binary64 normal value has an exponent between 0x001 and 0x7ffe (a 0x7ff indicates NaN or Inf). The significand can be any value (expect 0 if the exponent is zero).</p>
<dl class="section note"><dt>Note</dt><dd>This function will not raise VXSNAN or VXVC (FE_INVALID) exceptions. A normal double compare can.</dd></dl>
<table class="doxtable">
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<th align="right">processor</th><th align="center">Latency</th><th align="left">Throughput </th></tr>
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<td align="right">power8 </td><td align="center">6-15 </td><td align="left">1/cycle </td></tr>
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<td align="right">power9 </td><td align="center">5 </td><td align="left">1/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramname">vf64</td><td>a vector of __binary64 values. </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>a vector boolean long long, each containing all 0s(false) or 1s(true). </dd></dl>